esilicon-automated-gdsii-multi-project-wafer-quote-webinar-20141031

Details    Video

Webinar Video:
10-Minute GDSII
Tapeout Quotes

Replay of a live eSilicon webinar moderated by Dan Nenni (SemiWiki founder) where we demonstrate our GDSII quoting portal.  Working with a real customer, we generate a complete, executable quotation for a production GDSII tapeout at TSMC in about 10 minutes.  We also explore "what if" scenarios to optimize unit price for the program. Created: July 31, 2014, 8:00 AM PDT.

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Careers

eSilicon has revolutionized the chip business by partnering with tier-one suppliers to streamline the IC design and manufacturing processes, bringing our customers' chips to market faster. We are currently looking for creative, talented people to fill key positions around the world. This e-mail address is being protected from spambots. You need JavaScript enabled to view it today!

North America

Customer Solutions Engineering - Pre-Sales Engineer ASIC/IP/Packaging (San Jose, CA)

Updated on: July 22, 2014

Seeking an experienced, customer oriented, semiconductor (ASIC/IP) engineering professional who will act as a primary pre-sales resource in providing Comprehensive Technical Solutions to eSilicon Customers.

Responsibilities:

  • Primary customer interface for all technical support activities during the pre-sales process
  • Represent eSilicon’s technical expertise to current and potential customers
  • Work closely with eSilicon’s sales, marketing and technology groups to craft proposed solutions for customers
  • Align with IP suppliers to understand their products and benefits to eSilicon customers
  • Work with customers and IP suppliers to target best solutions
  • Work with IP suppliers on custom solutions or road map development as needed
  • Analyze eSilicon solutions as they relate to competition
  • Work closely with marketing to adjust proposals or roadmaps as needed
  • Develop technical presentations

Background and Skills:

Familiar with ASIC process technology:

  • Different technology nodes and relevant features
  • Experience with multiple foundries, with emphasis on TSMC
  • Experience with advanced process nodes – 28/16/14nm
  • Experience in large, complex design
  • Key performance metrics
  • Fabrication process
  • Prototype bring up
  • Production qualification process
  • Knowledge of failure analysis (FA) a plus
  • Experienced in ASIC physical design
  • Timing analysis using Static Timing Analysis (STA)
  • Floor planning
  • Place and Route
  • Clock tree architectural decisions and implementation
  • Timing closure
  • Timing signoff methodology
  • Low power techniques
  • Experienced in ASIC Design for Test (DFT)
  • Knowledge in IP
  • Familiar with foundation IP (standard cell libraries, IO, memory, PLL)
  • Familiar with common hard IP blocks (SerDes, MXS, processors)
  • Familiar with common soft IP blocks (memory controllers, SerDes controllers)
  • Packaging
  • Familiar with package technology
  • Can work with package engineering to select cost competitive solutions
  • Familiar with package and board level Signal Integrity analysis
  • Excellent communication skills, including written and presentation skills
  • Self-starter – able to craft solutions to complex problems with little to no input
  • BS EE Degree
  • Minimum 10 years’ experience as described above
  • Must be eligible to work in the US without restrictions
  • Travel required (~10%)

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Coming soon

Asia

ASIC Packaging Engineer (Ho Chi Minh City or Danang, Vietnam)

Updated on: August 12, 2014

eSilicon's Vietnam design team is seeking an experienced ASIC Design Engineer or PCB Design Engineer who will focus on package design.

Responsibilities:

  • This experienced digital or analog Design Engineer will be a member of the technical packaging team responsible for package planning, ASIC packaging design, development, design, power and signal integrity characterization.
  • Initial work will involve training in the field of advanced packaging including power and signal integrity.

Background and Skills:

  • Candidates must be skilled in scripting and possess a fair knowledge of ASIC physical design and/or PCB layout (3-5 years relevant experience)
  • Preference for background including simulation and layout
  • Knowledge of Allegro Package Designer (APD), extraction tools (PowerSI, XtractIM, HFSS), simulation tool (HSPICE) or similar preferred
  • Collaborative, enjoy interacting with customers as well as internal departments
  • BS/MSEE or equivalent
  • Fluent in English is required
  • Must be eligible to work in country of hire without any restriction(s)

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Analog Design Engineers (Ho Chi Minh City or Danang, Vietnam)

Updated on: September 4, 2014

Analog Design Engineers report to our Analog Mixed Signal (AMS) Managers and are members of the PHY team and support the design. These engineers will work on RTL design, verification or static timing analysis (STA) based on specific design situation.

Responsibilities:

  • RTL design
  • RTL synthesis
  • RTL/Verilog verification
  • Timing verification
  • DFT supporting tasks
  • Process/device/library study
  • Documentation
  • Script writing (Perl, C)

Background and Skills:

  • Bachelor/Master of Electronics or Electronics and Telecommunication
  • Preferably 3 or more years of experience in IC design field as described above
  • Familiar with design tools: SNPS DC/PT, HSPICE, Verilog and ModelSim
  • Good communication skills are required (Vietnamese and English)
  • Must be eligible to work in country of hire without restrictions

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Physical Design Engineers (Ho Chi Minh City, Vietnam)

Updated on: September 4, 2014

Reporting to a Back End Design Manager, our Physical Design Engineers’ primary responsibilities consists of the physical design flow from Netlist to GDSII, physical synthesis, verification and finalization for the design.

Responsibilities:

  • Audit customer design for PnR processing
  • Perform physical design flow from Netlist to GDSII with timing closure, DRC clean, audit Netlist/timing constraints, clock tree synthesis and hold fixing, and routing and post routing optimization.
  • Timing sign-off: Timing clean database with timing signoff tools
  • Synthesis and floor planning
  • Power structure designing

Background and Skills:

  • Bachelor/Master of Electronics or Electronics and Telecommunication
  • Hands on experience with detailed exposure to an actual SoC physical design in STA, floor-planning, power analysis, CTS, routing, DRC/LVS and noise analysis using Magma or Synopsys ASIC physical design tools.
  • Scripting language with Perl, Tk/Tcl, AWK, and Shell
  • Good communication skills are required (Vietnamese and English)
  • Must be eligible to work in country of hire without restrictions

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Test Development Engineers (Ho Chi Minh City or Danang, Vietnam)

Updated on: September 4, 2014

Responsibilities:

  • Work with design and DFT (Design For Test) engineers to define test coverage and methodology to support bring-up, debug and release to production of complex ASICs.
  • Responsible for comprehensive Test Plan development in conjunction with customers.
  • Responsible for ASIC/IC test development, test pattern generation and supporting silicon debug.
  • Interfacing closely with design, DFT, product, test, and quality and reliability engineers to resolve device, test, yield and customer issues.

Background and Skills:

  • Experience with a lab environment such as oscilloscopes, voltmeters, BERT, spectrum analyzers, etc.
  • Experience in test methodologies including memory BIST, scan, loopback and functional test pattern generation would be preferred.
  • Usage of simulation tools and test benches preferred.
  • Working knowledge of high speed or at-speed test for complex interfaces such as SerDes, DDR and mixed signal.
  • Preferred tools/languages/skills: C, Awk, Perl, Verilog, VHDL, basic knowledge of design, Linux/Unix, scripting, Excel, PowerPoint and Word.
  • ATE (Automatic Test Equipment) experience (Teradyne J750 and Verigy 93K beneficial) preferred.
  • BSEE/MSEE degree or equivalent.
  • Excellent interpersonal and communication skills required (Vietnamese and English).
  • Must be eligible to work in country of hire without restrictions.

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Circuit Design Engineers (Ho Chi Minh City or Danang, Vietnam)

Updated on: September 4, 2014

Our Circuit Design Engineers will join a team working on many different advanced memory technologies ROM/RAM/TCAM and more.

Responsibilities:

  • Responsible for integrated circuit design of IP macros including circuit and logic simulation
  • Perform design documentation and report
  • Circuit design using CAD tool (Cadence/Custom design)
  • Perform circuit verification using eSilicon QA/QC flow

Background and Skills:

  • Bachelor/Master of Electronics or Electronics and Telecommunication
  • Prefer two or more years of experience in IC design field
  • Strong background in semiconductor physics and logical analytics
  • Familiar in using circuit and logic simulation tools (Cadence/HSPICE/HSIM)
  • Good communication skills are required (Vietnamese and English)
  • Must be eligible to work in country of hire without restrictions

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Circuit Design Managers (Ho Chi Minh City or Danang, Vietnam)

Updated on: September 4, 2014

Our Circuit Design Managers have full line management responsibilities including resource development, managing through subordinate supervisors and/or directly managing design engineers to complete design work as assigned to the function including IP development, IP design services as well as design methodology and process development.

Responsibilities:

  • Manages a specific functional area including resources development such as setting objectives, providing guidance, direction and mentorship to staff, and being involved in the recruitment and training of engineering talent
  • Receives assignments in the form of goals and determines methods, techniques and resource allocation to meet those goals
  • Recommends changes to policies and establishes procedures that affect the function
  • Manages activities of diverse scope requiring an evaluation of a variety of factors
  • Develops and administers schedules and requirements; may have budget responsibilities
  • Acts as advisor to subordinate(s) to meet schedules and/or resolve technical problems
  • Interacts with subordinate supervisors or staff, customers, and peer managers involving cross functional matters

Background and Skills:

  • Bachelor/Master of Electronics or Electronics and Telecommunication
  • 5 or more years of experience in IC design field
  • Solid content knowledge in field of expertise and able to act as an advisor to the group and to proactively work toward problem resolution
  • Strong verbal and written communication skills and ability to influence effectively (Vietnamese and English)
  • Ability to manage professional employees (design engineers), to handle people management tasks, and to plan and execute work in pursuit of company goals and objectives
  • Ability to independently manage hiring, appraisal and discipline of subordinates (with appropriate management approvals)

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Europe

PHP Developers (Bucharest, Romania)

Updated on: June 20, 2014

Become part of eSilicon's eBusiness development team in building intranet and Internet tools. The position offers opportunity to work closely with the ASIC engineering, sales and marketing teams.

Responsibilities:

  • The PHP developer will primarily be hands-on coding for the company's applications, using:
    • LAMP stack development (PHP 5.3, MySQL)
    • REST APIs
    • Software design in OOP
    • UI implementation with jQuery, CSS, HTML5
  • Understand requirements and evaluate their implementation costs
  • Develop testable and maintainable code for long-term projects

Background and Skills:

  • BS or MS in Computer Science or equivalent and 6+ years in software development/engineering as described above, including:
    • Minimum 4 years in working with OOP
    • Minimum 4 years’ experience in PHP
    • Minimum 2 years’ experience with CSS, HTML, and JavaScript/jQuery
  • Experience in PHPUnit is a plus
  • Experience in MVC framework is a must
  • Fluency in English (speaking, reading and writing) is a must

To be considered for this position, please submit your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Note to Recruitment Firms, Agencies and Other Third Parties:
eSilicon does not accept unsolicited referrals or resumes of candidates and does not pay fees associated with unsolicited referrals or resumes. Unless a current, written, eSilicon-specific job order and search services agreement is signed by eSilicon and on file with eSilicon's human resources-talent acquisition organization, referrals and resumes from third parties are considered unsolicited.