SerDes Solutions from eSilicon
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Now available from eSilicon: Avago Technologies’ industry-proven, best-in-class SerDes cores. Avago Technologies’ SerDes, combined with eSilicon’s proven design, manufacturing and productization services, provides an unbeatable combination for the development and volume production of custom chips serving the growing storage, communications, and high-performance computing markets. |
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| Figure 1: Pre-DFE Rx Eye Measurement | Figure 2: Post-DFE Rx Eye Measurement | |
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Images provided by Avago Technologies, 10.3125 Gbps Backplane DFE Operation. Channel Description: 26cm Char board, >1 meter over FR4 backplane, 2 backplane connectors |
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The explosive growth of broadband data and video services among consumers has exponentially increased the processing and bandwidth requirements on the underlying networking, storage and computing infrastructure. System OEMs have to constantly upgrade their offerings by building higher speed interfaces on their ASICs while maintaining the same form-factor and power specification. Fabless Semiconductor Companies (FSC) have to offer similar high-speed interface capabilities in order to differentiate their products and stay competitive. Both System OEMs and FSCs look for state-of-the-art SerDes cores in order to reduce their design risk and lower the development cost.
Product Features
Now available in both 90nm and 65nm CMOS processes in TSMC foundry, these SerDes cores represent Avago Technologies' sixth generation of production-proven, high performance, multi-rate transceivers with best-in-class features such as:
- Rates from 1.0625 Gbps up to 10.51875 Gbps
- Exception signal integrity and jitter performance
- Adaptive decision-feedback equalizer (DFE) in receiver
- Programmable transmitter pre-emphasis
- Bit Error Rate (BER) of less than 10-17
- Targeted for operation over legacy (>30'' FR4) backplanes
- Optional proprietary encoding schemes
- Meets established industry standards such as XAUI, XFI (10Gigabit Ethernet), Fibre Channel and PCI Express
- More than 200 SerDes channels per die
- Advanced on-chip diagnostic intelligence
Market Requirements
System developers today depend on their ASIC’s high-speed transceivers’ capabilities in order to design products capable of handling multiples of 10Gigabits of line rates in high-performance systems.
- A typical 10G line card has several 10Gigabit links on line side coming over XFP modules using either XAUI x4 lanes or a single XFI interface.
- After passing through the standard MAC function, these data channels require additional packet processing and quality-of-service (QoS) functions before forwarding the traffic over a switch backplane.
- Most system vendors prefer to design custom ASICs to perform these functions in order to differentiate their solutions. Unique to each application, there are needs for high-speed chip-to-chip interconnect and links over backplanes ranging from 1.25Gbps to 10.3125Gbps.
- Moreover, standards based protocols support may dictate the link speeds. For example, in a 10G/20G line card application shown below, the data links are 3.125Gbps XAUI or 6.25Gbps CEI-6 interface. The backplane ASIC will need as many as 48 to 96 channels depending on the aggregate bandwidth of the line card. The control plane ASIC may have need for 4x or 8x PCI-Express Gen1 (2.5G) or Gen2 (5G) interfaces to connect to on-board CPU.
eSilicon’s High-Performance Solutions
eSilicon makes the integration of a wide range of data rates and a variety of protocols in their custom ASIC flow easy with the use of Avago Technologies’ high-performance multi-rate transceivers and an extensive portfolio of specialty 3rd party IP. Avago Technologies’ low-power slim design with state-of-the-art jitter performance allows integration of 48 to 96 channels on a single chip for low-cost server or networking system solutions using existing backplanes while maintaining the same power budget. Developing a customized design to your specific requirements has never been easier.
Avago Technologies’ Cores Description
eSilicon, through its agreement with Avago Technologies, offers a broad portfolio of SerDes cores for a variety of data-rates and protocol standards. Now you can select the right interface standard at the right speed in a given process node in order to build your own custom chip solution.
If you would like more information on these offerings, or have questions about other IP not featured here, please contact us. eSilicon has an extensive database of IP and can help find the right IP for your custom chip.
From process technology to semiconductor IP to implementation strategies, eSilicon enables you to get the results you want, when you want them.
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© 2008 eSilicon Corporation. All rights reserved. This publication is protected by copyright and international treaty. No part of this publication may be reproduced in any form by any means without prior written authorization from eSilicon Corporation. eSilicon and the eSilicon logo are registered trademarks and eSilicon Enterprise and Enabling Your Silicon Success are trademarks of eSilicon Corporation. Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the U.S. and other countries. Other trademarks mentioned herein are the property of their respective owners.
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