What is IC Design Virtualization?

Find out more with our IC design virtualization white paper series:

  • Design Virtualization and Its Impact on SoC Design

  • Design Virtualization Technology for Low-Power ASICs


TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.


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Design Virtualization and Its Impact on SoC Design

Advanced SoC projects present the designer with a large number of options for technology, IP, foundation libraries, memory and operating conditions. Finding the right combination is difficult as costly and time-consuming trial implementations are needed. This paper discusses a unique new approach to this problem called design virtualization.

Design Virtualization Technology for Low-Power ASICs

Chips can rarely meet their power budget if the whole chip is active all the time using a single library. So architectural design techniques have become very important. This paper discusses a variety of approaches for reducing power in an ASIC design, including something new: design virtualization technology.

From Medical and Wearables to Big Data: Differentiated IP for the IoT Spectrum

Whether it’s a tiny always-on medical device or a secure cloud network processing Big Data, the Internet of Things is bringing new challenges to IC design. This white paper provides IP examples and techniques for customizing memory IP to manage power and bandwidth demands in IoT applications.

High-Performance Network Data-Packet Classification Using Embedded Content-Addressable Memory (TCAMs)

With port speeds exceeding 100Gbps, route lookups that are fundamental to all routers have relied on ternary content addressable memories (TCAMs) to provide a lookup response within a clock cycle. However, TCAMs in discrete form are expensive, consume a lot of power, compete for precious real estate on the printed circuit board (PCB), and in some applications lack required flexibility. Embedding a TCAM block along with the rest of the system in a single device should overcome these disadvantages. This paper provides an overview of advantages of embedded TCAMs and describes a few applications that could particularly benefit from embedded TCAM technology.

Quantifying IP Entitlement for 14/16nm Technologies

Meeting the pressures of increased cost per transistor below 28nm won’t be easy, but memory compiler IP technology holds promise.

How to Improve the Profitability of Fabless Semiconductor Companies

This white paper explores several effective strategies available to meet the challenges of managing the complexity of the semiconductor manufacturing supply chain while increasing gross margin and enterprise value.

Viable Product Development at 22nm
Why an integrated value chain is becoming critical and where to find the necessary expertise to make all the pieces work together.

The end of classical scaling at 90nm and the introduction of a broad array of challenges that now have to be dealt with at every process node beyond 65nm has changed IC design forever. Design, manufacturing and production must be tied together more closely than ever in order to address the challenges of power, electrostatic discharge (ESD), electromagnetic interference (EMI), IP integration, complex packaging options and manufacturing yield. Few companies have the focused resources within each of these disciplines to successfully complete chips. Fabless semiconductor companies and medium-sized semiconductor companies that own their own fabs are forced to reconsider their business models looking outside for the high level of expertise required to complete the design and manufacture of chips.
High-Speed Bus Architecture and Data Transmission Technology Overview

High speed and low power embedded processors are used frequently in today's high performance networking and communication systems, digital consumer electronics, and office automation applications. It is extremely important for the equally fast I/O and multiprocessor busses to keep pace with them so as to enable an effective product solution. This report is intended to be a quick reference for a high level understanding of bus architectures, the most widely used data transmission standards and I/O bus solutions. It also includes an extensive glossary and set of references for further research.

WIP Tracking IC Manufacturing Workflow and Cycle-time Reduction

It is well known that talented product planners and engineers can achieve tremendous savings in time and money through their knowledge of the workflows and relationships in the integrated circuit (IC) manufacturing supply chain. This document describes the "prototype" and "mass production" workflows based on typical durations for the purposes of discussing Work-in-Progress (WIP) tracking and optimization. Written from the perspective of a fabless ASIC provider, this paper proposes that WIP tracking can reduce the cycle time from GDSII tape-out to the delivery of packaged and tested chips.

The Challenges of Creating a Successful Back-End Manufacturing Operations Flow

It is becoming very clear that outsourcing of the back-end manufacturing operations part of the IC development flow is economically beneficial to fabless semiconductor companies of all sizes. By outsourcing post-GDSII operations, fabless companies can concentrate on their core competency, which is chip design, by reallocating their costs from non-core competency skills to differentiating skills. The goal of this White Paper is to paint a realistic picture of the complexities of manufacturing operations in the era of deep sub-micron CMOS, and dispel certain simplistic notions about the back-end manufacturing flow.