Webinar Video: 10-Minute GDSII Tapeout Quotes

Replay of a live eSilicon webinar moderated by Dan Nenni (SemiWiki founder) where we demonstrate our GDSII quoting portal.  Working with a real customer, we generate a complete, executable quotation for a production GDSII tapeout at TSMC in about 10 minutes.  We also explore "what if" scenarios to optimize unit price for the program. Created: July 31, 2014, 8:00 AM PDT.

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TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

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Instant MPW Quotes: New Die Packaging Services

Request a free account and explore your multi-project wafer (MPW) production options with no obligation. Our newest MPW quoting tool includes standard IC package options.
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Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

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Quantifying IP Entitlement for 14/16nm Technologies

Meeting the pressures of increased cost per transistor below 28nm won’t be easy, but memory compiler IP technology holds promise.

How to Improve the Profitability of Fabless Semiconductor Companies

This white paper explores several effective strategies available to meet the challenges of managing the complexity of the semiconductor manufacturing supply chain while increasing gross margin and enterprise value.

Viable Product Development at 22nm
Why an integrated value chain is becoming critical and where to find the necessary expertise to make all the pieces work together.

The end of classical scaling at 90nm and the introduction of a broad array of challenges that now have to be dealt with at every process node beyond 65nm has changed IC design forever. Design, manufacturing and production must be tied together more closely than ever in order to address the challenges of power, electrostatic discharge (ESD), electromagnetic interference (EMI), IP integration, complex packaging options and manufacturing yield. Few companies have the focused resources within each of these disciplines to successfully complete chips. Fabless semiconductor companies and medium-sized semiconductor companies that own their own fabs are forced to reconsider their business models looking outside for the high level of expertise required to complete the design and manufacture of chips.
High-Speed Bus Architecture and Data Transmission Technology Overview

High speed and low power embedded processors are used frequently in today's high performance networking and communication systems, digital consumer electronics, and office automation applications. It is extremely important for the equally fast I/O and multiprocessor busses to keep pace with them so as to enable an effective product solution. This report is intended to be a quick reference for a high level understanding of bus architectures, the most widely used data transmission standards and I/O bus solutions. It also includes an extensive glossary and set of references for further research.

WIP Tracking IC Manufacturing Workflow and Cycle-time Reduction

It is well known that talented product planners and engineers can achieve tremendous savings in time and money through their knowledge of the workflows and relationships in the integrated circuit (IC) manufacturing supply chain. This document describes the "prototype" and "mass production" workflows based on typical durations for the purposes of discussing Work-in-Progress (WIP) tracking and optimization. Written from the perspective of a fabless ASIC provider, this paper proposes that WIP tracking can reduce the cycle time from GDSII tape-out to the delivery of packaged and tested chips.

The Challenges of Creating a Successful Back-End Manufacturing Operations Flow

It is becoming very clear that outsourcing of the back-end manufacturing operations part of the IC development flow is economically beneficial to fabless semiconductor companies of all sizes. By outsourcing post-GDSII operations, fabless companies can concentrate on their core competency, which is chip design, by reallocating their costs from non-core competency skills to differentiating skills. The goal of this White Paper is to paint a realistic picture of the complexities of manufacturing operations in the era of deep sub-micron CMOS, and dispel certain simplistic notions about the back-end manufacturing flow.

The Last Mile: Outsourcing Semiconductor Manufacturing Operations

Outsourcing is a concept that has a long positive history although the birth of each outsourcing phenomenon was not without pain. This whitepaper will discuss and explain the reasons why manufacturing operations outsourcing is a good business decision for many semiconductor companies. The whitepaper closes with a case study highlighting how a representative semiconductor company can focus on product innovation and new market creation and at the same time improve its financial strength through manufacturing operations outsourcing.

Strategies to Prevent IC Failures in Volume Production

When IC devices are produced and shipped to end customers, it is important that they will function as specified in the application environment. This paper outlines strategies and practices used to statistically sample, and predict how a device will operate over time. The practices outlined are believed to be best in class techniques for a successful product launch. These strategies most likely will point to sensitivities in devices that cause intermittent failures or process weaknesses which cause hard failures. If all of the outlined methods are not done in the preproduction phase, it may be necessary for failures to be analyzed later to prevent such occurrences in the future.