Details    Video


Details    Video

Webinar Video:
10-Minute GDSII
Tapeout Quotes

Replay of a live eSilicon webinar moderated by Dan Nenni (SemiWiki founder) where we demonstrate our GDSII quoting portal.  Working with a real customer, we generate a complete, executable quotation for a production GDSII tapeout at TSMC in about 10 minutes.  We also explore "what if" scenarios to optimize unit price for the program. Created: July 31, 2014, 8:00 AM PDT.


TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.


Instant MPW Quotes: New Die Packaging Services

Request a free account and explore your multi-project wafer (MPW) production options with no obligation. Our newest MPW quoting tool includes standard IC package options.
MPW shuttle service details>>>

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See Our Complete
IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

Subscribe to Package Matters blog

Package Matters, by Javier DeLaCruz, eSilicon's manufacturing technology director, covers hot topics in semiconductor packaging such as 3D-IC and 2.5D-IC packaging technology, thru-silicon-vias (TSVs), the relative cost of multi-chip modules (MCMs), and considerations for choosing the lowest-cost package for your ASIC. [Read More]


ASIC Design Services

ASIC design involves the complex interaction of foundry process technology, IP design and integration, EDA tools and design methodologies, physical design, design for test, package design and product engineering. We focus on optimizing for the combination of power, performance, and area (PPA) appropriate for your device's specific targets.

  • We have access to the leading foundry process technologies to 14/16nm through our partnerships with the world's leading-edge foundries.
  • In addition to our vast third-party IP portfolio — including IP from ARM, Avago Technologies, Imagination Technologies, Northwest Logic, Synopsys and True Circuits — we provide custom logic, memory, analog and I/O solutions to meet your specific needs, be they targeted for high performance or low power.
  • Our unique PPA-optimized design methodology is targeted to provide the best power, performance and area for your ASIC.

Concurrent Design for First-Time-Right ASICs

Close collaboration between our design, test, package, and process engineering teams results in a smooth transition of our designs to manufacture so that your design is testable and manufacturable with high yield. Our extensive experience with this holistic approach to ASIC design has yielded a proven track record of first-time-right designs and provides you with a quality ASIC solution and low total cost of ownership.

eSilicon® ASIC Design Ecosystem