What is IC Design Virtualization?

Find out more with our IC design virtualization white paper series:

  • Design Virtualization and Its Impact on SoC Design

  • Design Virtualization Technology for Low-Power ASICs


TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.


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Engagement Model

As shown in the diagrams below, our business model provides you with fully tested, packaged parts with the flexibility of your choice of design handoff. We support a variety of handoffs – RTL, netlist, placed gates, GDSII, and production (proven, tested parts) — are some of the most common ones. These handoffs give you the flexibility to focus on your core competencies. Our highly collaborative approach to ASIC design provides you continuous feedback on the state of your design and addresses design issues early in the process, for a high-quality design as well as a predictable schedule.

eSilicon ASIC Manufacturing Engagement Model

RTL Handoff

The RTL handoff model enables you to focus on your RTL design and verification and development of timing and power constraints. Our collaborative approach to ASIC design provides you early feedback on potential physical design problems so that you can address them up front rather than wait until later.

eSilicon RTL Handoff

Netlist Handoff

The netlist handoff is the most common entry point at eSilicon. It allows you to provide a fully verified synthesized netlist along with timing and power constraints. Our unique PPA-optimization methodology provides you with best-in-class choices for memories and standard-cell libraries to meet your ASIC power and performance requirements.

eSilicon Netlist Handoff

Placed-Gates Handoff

The placed-gates handoff model is ideal for designs that are aggressive in terms of performance. This allows you to perform physical synthesis and placement and optimize your initial margins to meet aggressive performance goals. It also allows you to make critical architectural decisions early in the physical design process to help avoid surprises later.

GDSII Handoff

The GDSII handoff model allows you to provide a tapeout-ready database. Our package and test engineers will work with you during the design phase to provide a smooth handoff to manufacturing. We address critical package design issues such as core-power bounce and simultaneous switching output (SSO) analysis with detailed electrical simulations for proper signal integrity of your packaged part. Our design-for-test (DFT) and test engineers collaborate with you in developing the test plan for your design so that your product will have good yield at production.

GDSII Handoff Model

Production Handoff (SMS)

The production handoff model allows you to focus on new product development while we manage the production of your existing designs. Through our Semiconductor Manufacturing Services (SMS) engagement model, we manage the supply chain and provide product engineering and yield management services for high-quality products. The power of our aggregation and supply-chain management skills provides you with a cost-effective solution.

Production Handoff Model