TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

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IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

White Paper

High-Performance Classification Using Embedded Ternary Content Addressable Memory (TCAM)

With port speeds exceeding 100Gbps, route lookups that are a fundamental application to all routers have relied on ternary content addressable memories (TCAM) to provide a lookup response within a clock cycle. However, these devices in “discrete form” suffer from limitations in terms of power, cost and real estate and to some extent lack the required flexibility. Embedding a TCAM block along with the rest of the system in a single device should overcome these disadvantages. This paper provides an overview of advantages of embedded TCAMs and describes a few applications that could take advantage of embedded TCAM technology. [View more white papers]

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Custom Embedded IP Brochures

eFlexCAM™ Custom Embedded
CAM Compilers

Binary and Ternary CAM (BCAM and TCAM) compilers in 28nm-180nm.

eFlex™ Custom Embedded
Memory IP

SRAM, ROM, MPRF, CAM, and cache custom memories.

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Register-File Memory Compilers

eSilicon has designed single-port and two-port register-file memory compilers catering to wide variety of market segments.

High-Speed Register Files for Networking and Communications

Networking and communications customers rely on the performance of eSilicon high-speed register files to meet the demanding wireline speed requirements of networking applications. These register files at 40nm and 28nm have enabled our networking customers to meet the requirements of their tier-one customers.

Low-Power, High-Performance Register Files for Wireless and Handheld

Wireless and handheld customers engage with eSilicon to develop low-power, high-performance register files that can meet the low battery life requirements of wireless and handheld devices, while at the same time deliver the level of performance required by state-of-the-art devices such as smart phones.

eSilicon’s philosophy for developing memories is to customize the memories to end-customer requirements. This usually involves turning on multiple knobs to tune the area, power, performance of register files per customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.

Area

Performance

Power Management

Testability

Functional Options

  • Aspect Ratio
  • Side Decode
  • Push-Rule Bit Cell
  • Low Vt for Highest Performance
  • Banking
  • Center Decode
  • Array Source Biasing
  • Periphery Shutdown
  • Complete Shutdown
  • Dual Rail
  • DVFS
  • Mixed Vt Periphery
  • High Vt Periphery
  • BIST Mux
  • Scan Flops
  • Synchronous Bypass
  • Read Stress
  • Write Stress
  • Column Redundancy
  • Row Redundancy
  • Bit Write
  • Pipelined Output

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