Register-File Memory Compilers
eSilicon has designed single-port and two-port register-file memory compilers catering to wide variety of market segments.
High-Speed Register Files for Networking and Communications
Networking and communications customers rely on the performance of eSilicon high-speed register files to meet the demanding wireline speed requirements of networking applications. These register files at 40nm and 28nm have enabled our networking customers to meet the requirements of their tier-one customers.
Low-Power, High-Performance Register Files for Wireless and Handheld
Wireless and handheld customers engage with eSilicon to develop low-power, high-performance register files that can meet the low battery life requirements of wireless and handheld devices, while at the same time deliver the level of performance required by state-of-the-art devices such as smart phones.
eSilicon’s philosophy for developing memories is to customize the memories to end-customer requirements. This usually involves turning on multiple knobs to tune the area, power, performance of register files per customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.
Area
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Performance
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Power Management
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Testability
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Functional Options
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- Aspect Ratio
- Side Decode
- Push-Rule Bit Cell
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- Low Vt for Highest Performance
- Banking
- Center Decode
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- Array Source Biasing
- Periphery Shutdown
- Complete Shutdown
- Dual Rail
- DVFS
- Mixed Vt Periphery
- High Vt Periphery
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- BIST Mux
- Scan Flops
- Synchronous Bypass
- Read Stress
- Write Stress
- Column Redundancy
- Row Redundancy
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- Bit Write
- Pipelined Output
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if you would like to learn more about our custom IP offering.
