What is IC Design Virtualization?

Find out more with our IC design virtualization white paper series:

  • Design Virtualization and Its Impact on SoC Design

  • Design Virtualization Technology for Low-Power ASICs


TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.


See Our Complete
IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at

Custom Embedded IP Brochures

eFlexCAM™ Custom Embedded
CAM Compilers

Binary and Ternary CAM (BCAM and TCAM) compilers in 28nm-180nm.

eFlex™ Custom Embedded
Memory IP

SRAM, ROM, MPRF, CAM, and cache custom memories.

Registration required to download brochures.

[View all brochures]

Register-File Memory Compilers

eSilicon has designed single-port and two-port register-file memory compilers catering to wide variety of market segments.

High-Speed Register Files for Networking and Communications

Networking and communications customers rely on the performance of eSilicon high-speed register files to meet the demanding wireline speed requirements of networking applications. These register files at 40nm and 28nm have enabled our networking customers to meet the requirements of their tier-one customers.

Low-Power, High-Performance Register Files for Wireless and Handheld

Wireless and handheld customers engage with eSilicon to develop low-power, high-performance register files that can meet the low battery life requirements of wireless and handheld devices, while at the same time deliver the level of performance required by state-of-the-art devices such as smart phones.

eSilicon’s philosophy for developing memories is to customize the memories to end-customer requirements. This usually involves turning on multiple knobs to tune the area, power, performance of register files per customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.



Power Management


Functional Options

  • Aspect Ratio
  • Side Decode
  • Push-Rule Bit Cell
  • Low Vt for Highest Performance
  • Banking
  • Center Decode
  • Array Source Biasing
  • Periphery Shutdown
  • Complete Shutdown
  • Dual Rail
  • DVFS
  • Mixed Vt Periphery
  • High Vt Periphery
  • BIST Mux
  • Scan Flops
  • Synchronous Bypass
  • Read Stress
  • Write Stress
  • Column Redundancy
  • Row Redundancy
  • Bit Write
  • Pipelined Output

Please contact us at  This e-mail address is being protected from spambots. You need JavaScript enabled to view it  if you would like to learn more about our custom IP offering.