What is IC Design Virtualization?

Find out more with our IC design virtualization white paper series:

  • Design Virtualization and Its Impact on SoC Design

  • Design Virtualization Technology for Low-Power ASICs


TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.


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IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at

CAST™ (Component Auto-generation System for Test chips) Services

CAST (Component Auto-generation System for Test chips) Services help users generate wide-range test structures for silicon technology development and complete test chips for immediate usage.

See our Value-Added Services.

Value-Added Services

Whatever the engagement level you choose to begin working with eSilicon, as shown in the diagram below, we provide the services shown below your engagment level. For example, a customer engaging with us at the netlist level automatically gets the benefit of all the production services that occur after the handoff, such as product engineering and yield improvement, plus signal integrity, package design and so on.

eSilicon Engagement Levels


There are times when designers are looking for special additional services over and above the norm and eSilicon can offer a range of capabilities here, too.

Custom 2.5D packaging is a revolutionary way to get “More than Moore” out of semiconductors, connecting different silicon die together in the same package without needing to combine everything into one monolithic piece of silicon. eSilicon is a leader in this field and can help with all aspects of your 2.5D IC project.

Sub-System Design Optimization

In many system-on-chip (SoC) cases, the company designing the chip wants to focus its resources on the key blocks that differentiate its products in the market. Although a processor and memory sub-system may be a necessary part of the SoC and must be implemented, the company doesn’t want to tie its key designers up with designing and even more importantly, validating this sub-system.

eSilicon can design and optimize a processor and memory sub-system to free up your designers to work on your critical system blocks. Our designers have access to, and experience with, a broad range of processors and peripherals and can quickly craft a sub-system that meets your system needs, whether you are at the leading edge of what is possible in performance with the latest cores or are interested in the lowest possible power in an older processing technology.

eSilicon has implemented and optimized sub-systems for customers across a wide variety of applications, such as consumer MP3 players, printers, industrial control applications, telecom switches and projectors. Process technologies used today range from state-of-the-art deep sub-micron to mature processes for low leakage. eSilicon has experience with a variety of processors, including those from ARM, Tensilica and Synopsys.

Custom 3D and 2.5D Packaging

Custom 2.5D Packaging

eSilicon has been in the forefront of 2.5D technology for years. Our first HBM1 connected devices were assembled in 2013 and we have been active in the space since then with organic interposer technology, silicon interposer technology, non-interposer-based technologies and the IP needed to enable this technology.
eSilicon started the MoZAIC™ program (Modular Z-Axis Integrated Circuit) in 2011, focused on enabling the IP, design capability, packaging and test methodologies and supply chain needed to ensure the lowest-risk, highest-performance device development.

eSilicon 2.5D Project on Organic Interposer



eSilicon 2.5D Concept


eSilicon is connected to all levels of the semiconductor manufacturing supply chain: fabs, test and assembly companies, EDA companies and design houses. If you are interested in doing your first 2.5D or 3D project, we can help you make the right decisions. eSilicon will manage the entire supply chain using the fabs and assembly and test houses that are ready for 2.5D and 3D-ICs. eSilicon is already active in 2.5D and expects to be an early adopter of production-ready 3D technology.

Automated Test-Chip Generation for Quicker Process Introductions: CAST™ Tool and Services

Quick process introductions, migrations and first-time-right silicon are critical. For foundries and integrated device manufacturers (IDMs), properly designed test chip can bridge the gap between process simulation and production to deliver a dramatic impact on time-to-market and yield levels of new process introductions.

eSilicon’s CAST™ (Component Auto-generation System for Test chips) tool and services can automate test-chip generation at any process node or technology:

  • Quickly generates a wide range of test chips to fine-tune new processes
  • Significantly reduces development time and costs
  • Automation eliminates errors introduced by hand coding

For more information, please download the CAST brochure (registration required) or contact your local eSilicon sales office.


Please contact us to discuss any of our value-added services.