TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

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CAST (Component Auto-generation System for Test chips) Services help users generate wide-range test structures for silicon technology development and complete test chips for immediate usage.

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Value-Added Services

Whatever the engagement level you choose to begin working with eSilicon, as shown in the diagram below, we provide the services shown below your engagment level. For example, a customer engaging with us at the netlist level automatically gets the benefit of all the production services that occur after the handoff, such as product engineering and yield improvement, plus signal integrity, package design and so on.

eSilicon Engagement Levels

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There are times when designers are looking for special additional services over and above the norm and eSilicon can offer a range of capabilities here, too.

  • Sub-system design optimization is a service that can be used in cases where a company designing an SoC wants to focus its resources on the key blocks that differentiate its products in the market. eSilicon can design and optimize a processor and memory sub-system to free up your designers to work on your critical system blocks.
  • Custom 3D packaging is a revolutionary way to get “More than Moore” out of semiconductors, connecting different silicon die together in the same package without needing to combine everything into one monolithic piece of silicon. eSilicon is a leader in this field and can help with all aspects of your 3D-IC project.
  • CAST™ (Component Auto-generation System for Test chips) services provide automation software to help the rapid generation of test chip modules to speed up process characterization. Typical users are IDMs or fabless semiconductor companies who customize the process technology they use and want to speed up the process of bringing up new technology nodes.

Sub-System Design Optimization

In many system-on-chip (SoC) cases, the company designing the chip wants to focus its resources on the key blocks that differentiate its products in the market. Although a processor and memory sub-system may be a necessary part of the SoC and must be implemented, the company doesn’t want to tie its key designers up with designing and even more importantly, validating this sub-system.

eSilicon can design and optimize a processor and memory sub-system to free up your designers to work on your critical system blocks. Our designers have access to, and experience with, a broad range of processors and peripherals and can quickly craft a sub-system that meets your system needs, whether you are at the leading edge of what is possible in performance with the latest cores or are interested in the lowest possible power in an older processing technology.

eSilicon has implemented and optimized sub-systems for customers across a wide variety of applications, such as consumer MP3 players, printers, industrial control applications, telecom switches and projectors. Process technologies used today range from state-of-the-art deep sub-micron to mature processes for low leakage. eSilicon has experience with a variety of processors, including those from ARM, Tensilica and Synopsys.

Custom 3D and 2.5D Packaging

Custom 3D packaging is a revolutionary way to get “More than Moore” out of semiconductors, connecting different silicon die together in the same package without needing to combine everything into one monolithic piece of silicon. eSilicon is a leader in this field and can help with all aspects of your 2.5D or 3D-IC project.

3D-IC is of interest to the majority of the industry, especially to companies whose volumes (or the certainty of achieving them) make it tough to justify a high NRE — typically several million dollars in a leading-edge technology node. 3D chips also offer the opportunity to combine heterogeneous technologies — for example, using 28nm for a standard microprocessor-based subsystem (which can be re-used in multiple designs), while using a more mature 65nm process with a much lower NRE for the customized portion of the logic, and 130nm for a mixed-signal function.

There are different needs and reasons for the interest in 3D in different application areas. For example, the mobile space is driven mostly by the potential benefits of reduced power and space.  The communications infrastructure and networking space, however, is driven by yield improvement and the ability to insert more memory than would be possible using monolithic devices.  Increasingly, companies in this space are also interested in the lower-power benefits.  Mobile devices need thin architectures and have very thin package requirements.  On the other hand, larger networking devices require thicker 3D-ICs or interposers in order to handle the flatness needed for larger die and side-by-side architectures of the devices.

Although full 3D-IC is forecasted to be ready in 2013, the so-called 2.5D approach using silicon interposers has been ready for prototyping since late 2010. A 2.5D-based product uses a piece of passive silicon called an interposer to act like a miniature PCB, onto which other chips are placed (Figure 3). As the interposer consists solely of passive silicon, it is matched in thermal expansion and hence reduces the mechanical stress on the active pieces of silicon.  This is expected to have beneficial long-term reliability effects for the active circuitry. eSilicon’s approach uses a standardized form of interposer and builds “Tiles” of active silicon on top.


eSilicon 3D-IC Concept

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The Tiles that form the basis of the 2.5D approach can include functions such as:

  • Microprocessor sub-systems
  • Memory
  • FPGAs
  • High-performance PHY functions
  • High-performance analog functions such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)

eSilicon 2.5D Concept

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eSilicon is connected to all levels of the semiconductor manufacturing supply chain: fabs, test and assembly companies, EDA companies and design houses. If you are interested in doing your first 2.5D or 3D project, we can help you make the right decisions. eSilicon will manage the entire supply chain using the fabs and assembly and test houses that are ready for 2.5D and 3D-ICs. eSilicon is already active in 2.5D and expects to be an early adopter of production-ready 3D technology.

Automated Test-Chip Generation for Quicker Process Introductions: CAST™ Tool and Services

Quick process introductions, migrations and first-time-right silicon are critical. For foundries and integrated device manufacturers (IDMs), properly designed test chip can bridge the gap between process simulation and production to deliver a dramatic impact on time-to-market and yield levels of new process introductions.

eSilicon’s CAST™ (Component Auto-generation System for Test chips) tool and services can automate test-chip generation at any process node or technology:

  • Quickly generates a wide range of test chips to fine-tune new processes
  • Significantly reduces development time and costs
  • Automation eliminates errors introduced by hand coding

For more information, please download the CAST brochure (registration required) or contact your local eSilicon sales office.

 

Please contact us to discuss any of our value-added services.