Webinar: 10-Minute GDSII Tapeout Quotes

Join eSilicon and SemiWiki for a webinar demonstrating eSilicon's new automated GDSII quoting tool.
July 31, 2014, 8:00 AM PDT.
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TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

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Instant MPW Quotes: New Die Packaging Services

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White Paper

High-Performance Classification Using Embedded Ternary Content Addressable Memory (TCAM)

With port speeds exceeding 100Gbps, route lookups that are a fundamental application to all routers have relied on ternary content addressable memories (TCAM) to provide a lookup response within a clock cycle. However, these devices in “discrete form” suffer from limitations in terms of power, cost and real estate and to some extent lack the required flexibility. Embedding a TCAM block along with the rest of the system in a single device should overcome these disadvantages. This paper provides an overview of advantages of embedded TCAMs and describes a few applications that could take advantage of embedded TCAM technology. [View more white papers]

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IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

Unique ASIC Design Methodology

Our power, performance, and area (PPA)-optimal ASIC design methodology is unique in the industry. Based on extensive analysis of foundry device characteristics, standard-cell libraries and memories, and building blocks used commonly in design, we can help you select the right standard cells, memories and IP for your design and achieve a significant improvement in PPA over traditional methods. In addition to this, our custom IP solutions provide further improvements in PPA, resulting in the right chip for your market. Our Intelligent Infrastructure includes a knowledge base that has been built with over 10 years of data drawn from over 275 successful designs.

The eSilicon® methodology provides:

  • The automation required for scalability and consistency that supports accurate results
  • The flexibility required to customize a specific aspect of the design flow, including custom IP development

Extensive design reviews with subject-matter experts manage the details of your design. Close and concurrent interactions with package and test engineering not only provide you a holistic solution, but also provide timely, top- quality results during manufacture.