Unique ASIC Design Methodology
Our power, performance, and area (PPA)-optimal ASIC design methodology is unique in the industry. Based on extensive analysis of foundry device characteristics, standard-cell libraries and memories, and building blocks used commonly in design, we can help you select the right standard cells, memories and IP for your design and achieve a significant improvement in PPA over traditional methods. In addition to this, our custom IP solutions provide further improvements in PPA, resulting in the right chip for your market. Our Intelligent Infrastructure includes a knowledge base that has been built with over 10 years of data drawn from over 275 successful designs.
The eSilicon® methodology provides:
- The automation required for scalability and consistency that supports accurate results
- The flexibility required to customize a specific aspect of the design flow, including custom IP development
Extensive design reviews with subject-matter experts manage the details of your design. Close and concurrent interactions with package and test engineering not only provide you a holistic solution, but also provide timely, top- quality results during manufacture.