Join Us at ISSCC 2019: 56G SerDes Over 5-Meter Cable
Flexible Network-Optimized 7nm IP Platform
Deep Learning Webinar Video: Custom Chips for AI
Media Coverage
Blog Review: Feb. 6
eSilicon’s Mike Gianfagna reminds us that while a chip may work, it’s only successful if it performs in the context of the delivered system. Semiconductor Engineering
Getting to 56G Takes The Right Stuff
Designing SerDes for 56G and 112G is complex and challenging. In fact, there are only a few companies with working silicon. eSilicon is one of them and made an announcement at DesignCon this year that highlights another huge challenge for these designs – how to test them and measure their performance. By Tom Simon SemiWiki
Week In Review: Design, Low Power
eSilicon teamed up with Wild River Technology on an advanced test system for 56/112G PAM4 operation using the upcoming IEEE P370 standard By Jesse Allen Semiconductor Engineering
Recent News
eSilicon builds momentum as a strong tier one FinFET ASIC supplier
Upcoming Events
ISSCC 2019
February 17-21 | San Francisco, CaliforniaThe International Solid-State Circuits Conference is the foremost global forum...
OFC 2019
March 3-7, 2019 | San Diego, CaliforniaThe Optical Networking and Communication Conference & Exhibition (OFC) is...
