New GSA Forum Article By eSilicon CEO Jack Harding
OFC Demo Video: 7nm HBM2 PHY at 2.4Gbps
OFC Demo Video: 7nm 56G SerDes Over 5-Meter Cable
Media Coverage
400G Ethernet test chip tapes out at 7nm from eSilicon
Rather than just respin their 56G SerDes, eSilicon decided to add the 112G SerDes, and at the same time use this vehicle for several other objectives. The gearbox in this chip contains 8 lanes of 56G SerDes and 4 lanes at 112G, allowing it to handle 400G Ethernet traffic. By Tom Simon SemiWiki
TSMC-Certified OIP Virtual Design Environment with Synopsys Tools Now Available on Google Cloud
Synopsys Cloud Solution now supports Google Cloud Platform for TSMC OIP VDE. TSMC has certified that GCP meets its stringent security and performance requirements. Synopsys and Google Cloud have helped eSilicon optimize its implementation of a cloud-based flow Synopsys Press Release
eSilicon Uses ANSYS Multiphysics Simulations to Achieve Silicon-to-System Success
eSilicon’s Mike Gianfagna, VP, marketing, and Teddy Lee, architect, signal and power integrity, explain how ANSYS simulation helps meet system-in-package signal integrity and power integrity targets. ANSYS | Video
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