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Flexible Network-Optimized 7nm IP Platform
Deep Learning Webinar Video: Custom Chips for AI
Media Coverage
eSilicon and SiFive partner for next-generation SerDes IP
New SerDes must operate in a wide variety of system configurations — backplane configurations, temperature/humidity extremes, connector types. All this requires configuration of the SerDes equalization functions so the SerDes will match its operating environment so it can deliver the best power and performance. DSP-based SerDes can be "tuned" to the operating environment whereas analog SerDes cannot. By Daniel Nenni SemiWiki
Week In Review: Design, Low Power
FPGA HLS flow; DSP-based SerDes; PCIe and NVMe debug; Ansys results. By Jesse Allen Semiconductor Engineering
eSilicon 7nm SerDes hits 56Gbps; neuASIC Platform includes AI accelerators for 2.5D/3D ICs
Using 7nm TSMC process technology, eSilicon has developed two high-performance platforms, including hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building AI accelerators in AI ASICs. By Mike Demler The Linley Group Microprocessor Report
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The Linley Group Microprocessor Report Details eSilicon 7nm IP
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September 18, 2018 | Menlo Park, CaliforniaThe GSA U.S. Executive Forum is an invitation-only event that brings together...
