I recently watched a webinar given by eSilicon, Wild River and Samtec about their project to enhance eSilicon's licensable SerDes solution for 56 and 112 Gigabit per second PAM4 & NRZ DSP-based SerDes family in 7nm.
By Randy Smith
Changes that sidestep von Neumann architecture could be key to low-power ML hardware. Research teams are looking at several possible ways to do in-memory processing. Some of them deploy digital techniques while others go for a mixed-signal approach.By Brian Bailey