COLLABORATE. DIFFERENTIATE. WIN.
How we do it
New data flow, higher switch density and IP integration create issues across the design flow.
By Ann Steffora Mutschler
"eSilicon has used Aprisa on several very large and complex FinFET chips across several process nodes, including 16nm and 14nm. We expect to apply the new release to our advanced 7nm work as well."
Sid Allman, eSilicon
Avatar Integrated Systems
AI and the design ecosystem; new approach to 56G SerDes; handling counters in formal; changes for OSATs.
By Jesse Allen
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eSilicon to demonstrate silicon performance of its 7nm 56G long-reach SerDes at ECOC, September 24-26, 2018
eSilicon Announces Availability of neuASIC IP Platform for AI ASIC Design
eSilicon to present power optimization paper at SNUG Singapore, September 21, 2018
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SC18 provides the leading technical program in the...
SemIsrael Expo 2018 brings together hundreds of Israeli semiconductor...
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