In this video from ITC 2018, eSilicon’s director of DFT Solutions, Joe Reynick, describes using Tessent products to test their large 2.5D deep-learning ASIC. They used hierarchical DFT for power control and to speed total DFT time. They achieved 30 percent yield improvement from memory repair. All DFT tests passed within four days at first-silicon bring-up.
Video by Mentor, a Siemens Business
Joe Reynick, director of DFT solutions at eSilicon, says that they used Tessent to solve issues affecting DFT (BIST, scan, boundary scan) and IP test (SerDes loop back, PLL test), for their large 2.5D deep learning ASIC. The presentation focuses on the application of hierarchical DFT and IP test.
Blog Post by Mentor, a Siemens Business