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Advanced ASICs are a Team Sport

By Mike Gianfagna on February 23, 2017 from

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in FinFET technologies, with an interposer, and multiple die, and never-before-proven ... continue reading

rush hour traffic analogy for the rush to prototype ICs for ISSCC

Rush Hour on the Technology Roadmap

By Mike Gianfagna on January 27, 2017 from

In a little over a week, the International Solid State Circuits Conference (ISSCC) will commence at the Marriott in downtown San Francisco. This prestigious conference showcases the latest semiconductor innovations from around the world. Looking at the advance program, one can’t help but notice a ... continue reading

act or wait photo

Designers: Take Control of Your Chip

By Mike Gianfagna on September 21, 2016 from

This is a familiar story for us – maybe it is for you, too. eSilicon engages with many companies on high-complexity ASICs. From time to time, a customer contacts us and says they have a design in mind, but they just can’t fit in the package, or meet the power budget, or meet timing. Fifty ... continue reading