56G 7nm SerDes: Eye-Witness Account
High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our 7nm, 56G long-reach SerDes. We were happy to report in that announcement: “lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality.” Anyone who has plugged a new and complex chip into a test fixture for the first time knows what this feels like.
There are a lot of unique features associated with our new SerDes. You can find a list of those at the link above and on our website if you want to learn more. What I want to discuss here is a road trip to Rome that is now winding down. We were at ECOC ─ 44th European Conference on Optical Communication. The topic sounds somewhat esoteric, but this is actually a very large show. If you’re an EDA aficionado, think of what the Design Automation Conference show floor looked like back in its heyday, only larger. Getting data from point A to point B is indeed big business.
Thanks to our partner, Anritsu, we were able to demonstrate, for the first time in public, our 7nm, 56G SerDes live. This was a very exciting time for our team. A bit about Anritsu for those not familiar with this space. They are a global provider of innovative communications test and measurement solutions. They’ve been around for 120 years (that’s not a misprint), with about 4,000 employees in over 90 countries. It seems that verifying that data gets from point A to point B is also big business.
For the geeks among us, here is the specific and detailed description of what we demonstrated, taken from our recent media advisory: “56G PAM4 data transfer running at 56Gb/s over two different BERTSCOPE channels with two different reaches, both driven by the Anritsu MP1900A Signal Quality Analyzer-R using a passive and an active PAM4 combiner. The demo with Anritsu is significant because it shows how it is possible to leverage TX finite impulse response (FIR) capabilities to increase performance and improve power figure of merit (FOM) and functionality.”
Back to the title, “eye-witness account.” Sorry, that was a misleading play on words. I didn’t actually fly to Rome to see this demo (although that would have been nice). Rather, I am reporting about the eye diagram we were able to create at the show. Eye diagrams are data traces that are used to measure compliance for high-speed serial links. An open “eye” means a stable signal with a low error rate. Newer SerDes, including ours, are no longer analog in nature. Rather, they are based on digital sampling and digital signal processing techniques. The challenge with this newer architecture is that it’s typically very difficult to construct an eye diagram without increasing the power and area of the device. However, eSilicon’s design team has figured out how to do this with NO increase in power or area. Just some of the secret sauce in the product. You can see the generated eye diagram from Rome in the photo, above.
If you’d like to follow our progress on this new IP, we’ve instituted a new blog on our site, “Platform Pages, Tales of IP Innovation.” We’d love to hear from you.