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Advanced ASICs are a Team Sport

By Mike Gianfagna on 02/23/2017
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The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in FinFET technologies, with an interposer, and multiple die, and never-before-proven throughput rates. For these kind of advanced technologies, it does take a village. What works is open, transparent collaboration.

collaborative ASIC design image

It starts with the customer, who knows the system application best. Their insights into system requirements, coupled with their intimate knowledge of the design itself, are absolutely critical. Innovation often takes the form of better methods to analyze and communicate. Let’s be clear – designs of this type do not proceed without surprises and challenges. The margin of victory is not avoiding these challenges, but rather developing an open, efficient and highly optimized way to deal with them.

And then there’s the supply chain ecosystem. The extended family if you like. Collaboration among these companies is just as critical for a successful project. How does high-performance IP interact with the rest of the chip at a new process node? How does a new process node impact overall throughput? How can we integrate and reliably test a collection of devices on a substrate? And how do we finally package the whole system in a reliable and cost-effective manner? Without open communication and a collaborative approach to problem-solving, none of this would work in a commercially viable way.

eSilicon is living this process every day. Along with our partners, we are excited to be able to share how this all works. On March 8, eSilicon, Rambus and Samsung Foundry will jointly present their capabilities, with a focus on how it all fits together to deliver advanced ASIC designs. 56G SerDes interfaces, HBM2 memory stacks, 2.5D integration and FinFET processes are just some of the advanced technologies that will be discussed. I encourage you to come to the event – it will be at the least educational and perhaps inspirational. It’s from 4PM – 7PM at Samsung’s new (and very cool) San Jose headquarters. We’ll top the evening off with some wine, beer and appetizers as well. You can check it out and register here.  Hope to see you there.

Live seminar: Succeeding with 56G SerDes, HBM2, 2.5D and FinFET