Designers: Take Control of Your Chip
This is a familiar story for us – maybe it is for you, too. eSilicon engages with many companies on high-complexity ASICs. From time to time, a customer contacts us and says they have a design in mind, but they just can’t fit in the package, or meet the power budget, or meet timing. Fifty percent or more of the area for many of the chips we see is composed of memory. So we start there. After a Pareto analysis of the memory sub-system, we typically find a few memory blocks that are causing all the closure grief. We have a significant memory design team, so we propose to re-design the problem memory blocks to cure the problem. We win business because of this capability.
When you look at this problem, the question comes up – why did the designer get into trouble with the memory sub-system in the first place? Looking into this question uncovers a few issues. First, the SoC design flows in use today have substantial abilities to dynamically optimize the logic portion of the chip for area, power and performance. The memory part of the chip design flow is more static however, with very little dynamic optimization capability. Fixing this weakness in the design flow is a topic for another day. Given this situation, the up-front choices made for the memory sub-system become very important. But finding the right memory sub-system requires a lot of exploration.
Many small memories, a few large memories, technology options, operating conditions and different memory architectures are all dimensions to be explored. One may be able to download front-end memory models from some of the larger vendors, but running the cases needed to compare them takes time – and time is something most designers don’t have a lot of. Unambiguously communicating to the purchasing team what is needed for a design is also challenging, as is the paperwork and logistics associated with this process. All this suggests the designer must cut corners to get the best information possible in the time available, and then move on.
There is a better way, and the internet plays a role.
Silicon has been building an online platform for semiconductor design and manufacturing over the past three years. The STAR platform provides users the ability to browse IP, reserve and implement prototype designs with multi-project wafer technology, tapeout a production chip and monitor the manufacturing process, all online, all the time. The Navigator tool has allowed designers to browse our memory and I/O IP online, compare implementation options and architectures, and download front-end views to try things out. All for free. With the rich library of pre-loaded information available on Navigator, a designer can typically explore all the options for a memory sub-system in an afternoon, without ever leaving their desk or talking to another human.
There was a gap, however.
That gap was the “last mile” if you will. Once a designer found IP that worked for them, the quoting and purchase of that IP fell back to conventional, non-online means. More delay, and opportunity for miscommunication. We recently fixed that piece. The designer can now get automated quotes online for the IP they’re interested in with Navigator. And once they have a PO, they can upload it to Navigator and download the back-end views for their IP, all online. This new online IP procurement system allows designers to take control of the memory specification and procurement process. And we believe that will result in better designs in less time. If you’re facing a memory sub-system design challenge, visit our website to learn more about Navigator. If you don’t yet have an account, you can get one here and try out the online tools, including Navigator. Take control of your design process, you’ll be glad you did.