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High-Speed Communication Takes a Village

By Mike Gianfagna on 01/31/2019
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Supply chain, partner network, ecosystem. There are a lot of ways to describe the collection of companies needed to get something done. We’ve all discussed the extensive ecosystem needed to get an advanced chip designed and built. Without a doubt, that is a formidable problem addressed by a sophisticated team of companies. I’d like to take it up a notch in this discussion, however. What about achieving ultra-high performance at the system level? There is an advanced chip or two in there for sure. But there’s a lot more. More players, more uncertainty, more challenges. A bigger ecosystem, one as big as a village.

Let’s examine these challenges from the perspective of backplane design for hyperscale computer systems — a popular topic these days. I’ve written about our 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes in the past. That’s a key part of the equation. We’ve set a high bar recently regarding what long reach means. More on that later. I’d like to explore what it really takes achieve these transmission speeds and error rates and what it takes to validate that the whole thing really works.

Forget the notion of a simple test fixture. This stuff is a lot more complicated than that. It starts with a specification — the complex set of capabilities required to “hit the target.” In this case, it’s the emerging IEEE P370 standard. According to the official website: “The standard is applicable to: PCB and related interconnects (including package, connector, cable, etc.) used in high-speed digital applications, operating with signals at frequencies up to 50 GHz.” To validate the performance of our 56G SerDes, we set out to build a test board that conformed to this specification.

Our journey began with Wild River Technology, a company that specializes in this area. And the collaboration grew from there. Keysight’s Advanced Design System was used to explore power spectral density. The core of the design utilized Samtec’s Bulls Eye® Test Point System, and two field solvers, ANSYS® HFSS™ and Simbeor THz also played a roll. When the design came together, we had a board that showcased our 56G SerDes performance over a long-reach channel quite well. As you read this, we’ll be wrapping up a two-day exhibition of the new board in the Samtec booth (#737) at DesignCon in Santa Clara.

eSilicon/Wild River Technology 56G SerDes evaluation board
eSilicon & Wild River Technology advanced SerDes test system will be demonstrated at DesignCon 2019 in Samtec booth #737: >2Tbps through >5 meters of copper cable

You might be thinking, “wow, that’s a lot of companies just to build a test board.” Yes, it is a lot, but all necessary to achieve the goal — delivered performance in the system. This should be the goal of any ASIC project. A working chip is an important step toward the goal, but it’s not the goal. Unless that chip can deliver the required performance in the context of the delivered system, the project isn’t a success, and delivering that level of accomplishment takes a collaborative attitude on the part of many ecosystem players.

At eSilicon, we’re always looking for ways to raise the bar for performance and find the right team of partners to deliver that performance. At the recent DesignCon event, we demonstrated our 56G SerDes across an eye-popping five-meter cable. Thanks to our new test board, the noise margins and performance were better than the last time we did this. At five meters, we are clearly “reaching beyond the rack” when it comes to backplane design. We’re not done yet, however. What if we could reach farther? How would that impact backplane design for hyperscale datacenter equipment? Keep watching to learn more.