Training as a Strategic Weapon

By Mike Gianfagna on 08/24/2017

In my last post, I discussed the topic of applying machine learning to the design of machine learning chips.  I pointed out that one can achieve significant improvements in schedule predictability, PPA compliance and an overall reduction in program risk if machine learning is applied to the right kind of knowledge base. This is very real, and we are seeing the benefits of this approach daily. But it’s not enough.

Predicting design hot spots and optimizing process and IP choices can have a huge impact on the outcome of a complex FinFET ASIC project. So can optimal use of compute, storage and EDA license resources. All of these techniques address the question of WHAT to use for the design. They do NOT address the question of HOW to do the design, however.

To cover this second part, one must consider different processes and technologies. The conventional approach to the HOW part of design has traditionally been addressed by design flows, documentation and on-the-job training. The “cook book” approach, if you like. While this can work quite well for mainstream designs with a high degree of repeatability, it doesn’t map very well to leading-edge designs. These types of designs are characterized by ultra-high complexity and substantial variability. Each of these designs is typically doing something for the first time.

FinFET ASIC design flow training image

When you’re operating in this kind of environment, repeatability helps – the reuse of a memory subsystem for example. However, one cannot count on repeatability as a single strategy for risk reduction.  Rather, one must leverage past lessons learned in a way that allows extrapolation to new problem-solving. For example, leveraging SerDes design knowledge to build new chip-to-chip interfaces. This combination of baseline reuse and extrapolated problem-solving creates a very new environment to address HOW to design.

In our experience, on the job training for this kind situation is not scalable. The intellectual insights required to leverage past learning for future problem-solving is a rare skill, but one that must be propagated efficiently. This has given rise to new training techniques. The best analogy here is the wave of “driver assist” features we are seeing in new automobiles. Today’s cars won’t allow you to take your hands off the wheel, look away and carry on a conversation. Recent advances will, however, automatically apply the brakes if the car “sees” something before the driver does. It is this kind of assisted problem-solving that allows one to capture the rare skills of the expert designer and make it available to a wide range of engineering talent.

So, design flow training can indeed become a strategic differentiator. A correctly facilitated process can create a design team in which ALL members possess the rare skills of insightful problem-solving, and that can be the margin of victory for advanced FinFET ASIC design.