5m Prototype Samtec EBCM Series ExaMAX® Backplane Cable Assembly

High-Speed Serial Comms, Getting There is Half the Fun

By Mike Gianfagna on October 25, 2018 from

Last month I wrote about our 56G SerDes announcement – silicon validated and running in Rome at a major show. We had a great time at that show and got a lot of compliments about the quality and flexibility of our SerDes.  These kind of unfiltered, unsolicited customer comments are really what ... continue reading

ECOC 2018, eSilicon 56G SerDes demo, eye diagram, in Anritsu's booth

56G 7nm SerDes: Eye-Witness Account

By Mike Gianfagna on September 27, 2018 from

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon ... continue reading

collaborative ASIC design image

Advanced ASICs are a Team Sport

By Mike Gianfagna on February 23, 2017 from

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in FinFET technologies, with an interposer, and multiple die, and never-before-proven ... continue reading