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ASICs Unlock Deep Learning Innovation: Live, In-Person Seminar

March 14, 2018 | Computer History Museum

Deep learning algorithms, powered by neural nets, hold promise to automate our world in ways previously reserved for science fiction. Computers and cell phones that recognize us and talk to us, along with cars that drive us are just a few of the revolutionary products on the near horizon.

Practical implementation of this technology demands extreme performance, low power and efficient access to massive amounts of data. Advanced ASICs play a critical role in the path to production for these innovations. In fact, many applications cannot be realized without the performance and security that a custom chip provides.

What is needed is an implementation platform supporting 14nm and 7nm FinFET process nodes to address the challenges of deep learning.

Please join Samsung Electronics, Amkor, eSilicon and Northwest Logic as we explore a complete implementation platform for deep learning ASICs.  The event will begin with a keynote address, Architecting the Future of Deep Learning, by Ty Garibay, CTO of Arteris IP.

There is no charge to attend this live, in-person deep learning seminar and networking event.

March 14, 2018
3:30PM – 7:30PM
Computer History Museum
1401 N Shoreline Blvd.
Mountain View, CA 94043
Registration

Agenda
3:30 Arrive and check in
4:00 Keynote presentation (newly added, details below)
4:30 Samsung Electronics: HBM2 memory solutions
5:00 Amkor: Advanced packaging solutions
5:30 eSilicon: ASIC/2.5D design and enabling 7/14nm IP platforms(HBM2 PHY, SerDes, TCAM, custom memories)
6:00 Northwest Logic: HBM controller
6:30 Networking reception (wine, beer, light food and lucky draw prizes)
7:30 Event ends

AI seminar registration form

Keynote Address: “Architecting the Future of Deep Learning”

Ty Garibay, CTO of Arteris IP, will discuss emerging applications of deep learning and how semiconductor technology can enable these innovations.

Mr. Garibay has played key roles in the development of microprocessor and SoC architectures and technologies, serving in architecture and design leadership roles at Motorola, Cyrix, SGI, and Alchemy Semiconductor. He managed ARM’s Austin Design Center and also ARM cores development and IC Engineering for Texas Instruments’ OMAP application processors group. Prior to joining Arteris IP, Mr. Garibay was VP of IC Engineering for Altera, and later led FPGA design in Intel’s Programmable Solutions Group. Mr. Garibay has authored and co-authored 34 patents, and has been published in multiple technical journals and conferences.