Design Automation Conference 2018
June 24-28, 2018 | San Francisco, California
Join eSilicon at DAC 2018:
55th Design Automation Conference
|eSilicon is proud to be a co-sponsor of the Stars of IP Party at DAC 2018
Tuesday, June 26, 7:00-11:00 PM
Stars of IP is a private, invitation-only event. eSilicon is proud to be a co-host for this event. Silvaco encourages interested parties to seek out eSilion or other co-hosts on the DAC exhibit floor to connect and inquire about a ticket.
|Mentor Panel Discussion:
Getting Your Tapeout Done on Time isn’t Easy, but It can be Easier
More than 50% of tapeouts don’t occur on schedule. Which 50% do you want to be in? Come listen to Calibre customers talk about the challenges that they face and the steps that they take to get their tapeouts on time.
Prasad Subramaniam, eSilicon’s VP, R&D and Design Technology, will join the panel, as well as Bob Stear from Samsung and Satish Dinavahi from Qualcomm India.
Tuesday June 26, 4:00-5:00 PM
DAC Pavilion #2161
|Samsung SAFE Partner Theater
eSilicon’s 14LPP IP Platform
Examples of production-qualified HBM/2.5D FinFET networking ASICs, including memory strategies to improve cost, density, power and yield.
Presenter: Mike Gianfagna, eSilicon’s VP, marketing
Tuesday, June 26, 3:00-3:15 PM
SAFE Theatre, Samsung Booth 2635
|ChipEstimate.com IP Talks!
Highly configurable 7nm IP platform for ASICs in the datacenter
eSilicon’s new 7nm IP platform for high-performance networking ASICs sets a new standard for configurability to achieve the demanding power, performance and density requirements of networking ASICs in less time and with better results.
Presenter: Hugh Durdan, eSilicon’s VP, strategy and products
Tuesday, June 26, 2:00-2:15 PM
ChipEstimate.com Booth 2134
Visit the Design Automation Conference 2018 website for the latest information.