DesignCon 2019 in Santa Clara, CA

DesignCon 2019

January 29-31 | Santa Clara, California

DesignCon 2019 is in Santa Clara for its 24th year. Created by engineers for engineers, this annual mega event brings together nearly 5,000 professionals from the high-speed communications and semiconductor communities for three jam-packed days of education and activities. As the nation’s largest event for chip, board, and systems designers, DesignCon is a must-attend opportunity to share ideas, overcome challenges, and source solutions.

Through an in-depth 15-track conference program — curated by a 99-person Technical Program Committee — and an expo showcase featuring today’s top exhibitors offering cutting-edge solutions on test and measurement equipment, electrical components, connectors, signal integrity and more, this event offers everything you need to connect with like-minded peers, deepen your education, and push your projects over the finish line.

eSilicon at DesignCon 2019

Panel Discussion:
Test Fixture Signal Integrity for 112G PAM-4: Lively Panel Discussion on the Top Design Rules
Wednesday, January 30
10:00-10:45 AM
Panelists: Tim Horel, eSilicon; Scott McMorrow, Samtec; Al Neves, Wild River Technology; Heidi Barnes, Keysight; Jason Ellison, Amphenol.

eSilicon 7nm 56G SerDes over 5-Meter Samtec Backplane Cable 
eSilicon and Samtec will demonstrate true long-reach capability for the most demanding system environments in next-generation 25 and 50 Tb/s switches with eSilicon 7nm 56G SerDes and 5-meter ExaMAX® Backplane Cable Assembly. Developers can accelerate their time to market with a high-performance, flexible, easy-to-configure SerDes that targets all of the common Ethernet, Fibre Channel and CPRI standards as well as proprietary rates common in data center and 5G wireless infrastructure applications.

The demonstration will be conducted in Samtec booth #737 at DesignCon 2019.

What you’ll see

  • First-to-market full DSP (Tx and Rx) 56G SerDes in 7nm with true long-reach performance for use in the most challenging backplane applications
  • Design flexibility through a unique clocking architecture and firmware-controlled design
  • Meet your PPA targets with superior performance and power efficiency
  • Build a robust system with demonstrated operation in 56G PAM4 over a 30dB backplane without forward error correction (FEC) & operation over a five-meter cable
  • Reduce time to market with our revolutionary graphical user interface (GUI) that allows quick, easy bring-up and system validation. From the GUI, users can access all the monitoring features such as non-destructive eye diagrams, SNR & BER, bathtubs, histograms and power measurements

The SerDes is part of eSilicon’s complete, highly configurable, FinFET-class 7nm networking IP platform.