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Hot Chips 2019: A Symposium on High-Performance Chips

August 18-20, 2019 | Palo Alto, California

Since it started in 1989, Hot Chips has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity, Silicon Valley. Hot Chips 2019 will be held at Stanford University in Palo Alto, California.

The Hot Chips 2019 conference typically attracts more than 500 attendees from all over the world. It provides an opportunity for chip designers, computer architects, system engineers, press and analysts, as well as attendees from national laboratories and academia to mix, mingle and see presentations on the latest technologies and products. The three days of the conference typically feature two tutorials, two keynotes, a panel discussion and around 25 presentations on a variety of subjects related to microprocessors and integrated circuits.

eSilicon at Hot Chips 2019:
neuASIC 7nm Platform for Machine Learning ASIC Design

Stop by eSilicon’s table to hear the latest on our 7nm neuASIC™ platform for machine learning ASIC design. Through customized, targeted 7nm FinFET IP and a modular design methodology, the neuASIC platform removes the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators. With the use of a Design Profiler and AI Engine Explorer, eSilicon-developed and third-party IP can be configured as AI “tiles” via an ASIC Chassis Builder, allowing early power, performance and area (PPA) analysis of various candidate architectures.

eSilicon neuASIC Machine Learning ASIC Platform
eSilicon neuASIC Machine Learning ASIC Platform Architecture


eSilicon neuASIC AI ASIC Platform Tile Diagram
eSilicon neuASIC AI ASIC Platform Tile Diagram: Scalable ASIC Architecture Based on Tiles


eSilicon neuASIC Available Compiled, Hardened & Verified 7nm AI Functions for AI ASICs
eSilicon neuASIC Platform: Available Compiled, Hardened & Verified 7nm AI Functions for AI ASICs


If you want to learn more about our neuASIC AI chip platform before Hot Chips 2019 in August, please contact