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International Test Conference 2018

October 28-November 2 | Phoenix, Arizona

International Test Conference (ITC) is the world’s premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.

eSilicon at ITC

Joseph Reynick, director, DFT Solutions, eSilicon will deliver two DFT-related presentations at ITC on October 30 and 31, 2018.

DFT and IP Test Methods for a Deep Learning IC

Mentor’s Diamond Supporter Session
Test for the Autonomous Age
The presentations will focus on three key test challenges IC vendors face as they make the promises of the autonomous age a reality. Joseph Reynick, eSilicon will be joined by Janusz Rajski, Mentor, A Siemens Business and William Howell, Intel. Other topics include:

  • Achieving high test quality and fast yield ramps with advanced process technologies incorporating 3D transistors
  • Strategies for meeting the requirements of a growing number of market segments like automotive that have strict quality and functional safety requirements

Tuesday, 10/30/2018, 10:45 AM MST, immediately following the opening keynote session in the Ballroom

DFT Considerations and Flow for Large 2.5D/3D Devices

Special Session 3.1: Testing of Gigascale Designs
Traditional IC DFT engineers must expand their horizons to include the details of packaging, physical design, test hardware, and even board-level test techniques when working with large 2.5D/3D system–in-package (SiP) devices. The planning, implementation and test for such a SiP is discussed in this presentation. Our discussion will also include challenges, solutions and potential areas for new opportunities in supporting 2.5D/3D technologies in the future.

Wednesday, 10/31/2018, 10:30 AM MST