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ISSCC 2019

February 17-21 | San Francisco, California

The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency and to network with leading experts.

eSilicon at ISSCC 2019

Monday, February 18
2:30-3:00 PM Paper Presentation
5:00-7:00 PM Demonstration
Session 6.3
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
eSilicon will demonstrate a fully functional SerDes in 7nm operating on multiple lanes, supporting multiple protocols. Some of the capabilities demonstrated include error-free NRZ communication, error-free PAM-4 communication, a transmitter eye diagram with five taps of equalization and a receiver eye diagram over multiple channels and different frequencies.

The paper and demonstration will be presented by Matteo Pisati, senior manager, analog IC design; Paolo Pascale, senior manager SerDes digital; and Fernando De Bernardinis, senior system and algorithm manager.

Additional authors include C. Nani, M. Sosio, E. Pozzati, N. Ghittori, F. Magni, M. Garampazzi, G. Bollati, A. Milani, A. Minuti, F. Giunco, P. Uggetti, I. Fabiano, N. Codega, A. Bosi, N. Carta, D. Pellicone, G. Spelgatti, M. Cutrupi, A. Rossini, R. Massolini, G. Cesura,  and I. Bietti, all of eSilicon Italy in Pavia, Italy.

Session 6: Ultra-High-Speed Wireline
Session Chair: Tony Chan Carusone, University of Toronto, Toronto, Canada
Associate Chair: Takayuki Shibasaki, Fujitsu Laboratories, Kawasaki, Japan

ISSCC 2019 Advance Program PDF