Linley Spring Processor Conference 2019
April 10-11 | Santa Clara, California
The Linley Spring Processor Conference 2019 is the only one of its kind focused on the processors and IP cores used in deep learning, embedded, communications, IoT, and server designs. The Linley Group will open the conference with an overview of the market, technologies, equipment-design, and silicon trends. The second day will start with a keynote from an industry leader to be announced. The remainder of the program will include talks and panel discussions covering a broad range of topics.
eSilicon at the Linley Spring Processor Conference 2019
Presentation & Panel Discussion
Thursday, April 11, 1:15-2:45
Session 5: SoC Design
Carlos Macian, senior director AI strategy and products will present:
Opposites Attract: Customizing and Standardizing IP Platforms for ASIC Differentiation
IP are fundamental building blocks of modern ASICs, often providing a competitive edge in spite of their standard nature. And yet, true differentiation and optimization mandates IP customization for the specific product needs. The challenge is how to combine standardization and ease of integration for an accelerated and predictable schedule with the need to optimize the IP. We will explore an approach to this problem using best-in-class, silicon-proven IP that is also designed for ease of integration and application-specific customization.
N7 SerDes Demonstrations
Wednesday, April 10, 4:45-6:15
Using Samtec ExaMAX backplane connector paddle cards and a five-meter ExaMAX backplane cable assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes.
The demonstration will drive four high-speed SerDes lanes in three configurations with point-to-point links:
- CPRI NRZ modulation
- 50G Ethernet PAM4 modulation
- 56 Gbps PAM4 modulation
Real-time data associated with all channels will be displayed to demonstrate the robustness and low power of the device:
- Voltage histograms, pre- and post-DSP
- Signal-to-noise ratio (SNR)
- Eye diagrams
- Bit error rate (BER) monitor
Stop by the demo during the reception on April 10 to learn more about our 7nm advanced IP.
- neuASIC™ 7nm platform for machine learning ASIC design
- 7nm FinFET-class IP platform for networking, high-performance computing, AI and 5G infrastructure