March 3-7, 2019 | San Diego, California
The Optical Networking and Communication Conference & Exhibition (OFC) is the largest global conference and exhibition for optical communications and networking professionals.
eSilicon at OFC 2019: Booth 5416
SerDes secrets revealed in private presentations
Live demos: 7nm 56G full DSP long-reach SerDes
Using Samtec ExaMAX™ Backplane Connector paddle cards and a five-meter ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes.
The demonstration will drive eight high-speed SerDes lanes in three configurations:
- PAM4 modulation with point-to-point links
- NRZ modulation with point-to-point links
- PAM4 modulation with double-length (10 meter) loop-back links with repeater
All channels will be run at different speeds to showcase the flexibility of the SerDes device. Real-time data associated with all channels will also be displayed to demonstrate the robustness and low power of the device, including:
- Voltage histograms, pre- and post-DSP
- Signal-to-noise ratio
- Eye diagrams
- Error rate plots
Live demos: 2.4Gbps HBM2 PHY subsystem for high-performance computing, networking & AI
This demonstration shows a complete high-bandwidth memory Gen2 (HBM2) solution in 7nm operating at 2.4Gbps.
- The subsystem includes:
- eSilicon’s latest 7nm HBM2 PHY
- Northwest Logic memory controller
- HBM DRAM stack from a leading memory supplier
- The test chip uses leading-edge interposer technology to interconnect the integrated PHY and controller with the 3D DRAM stack
- The firmware, combined with a user-friendly graphical interface (GUI), allows test and validation of the HBM subsystem
- Among other tests and monitoring tools available, this board demonstrates the link margin of the complete subsystem with the internal eye monitor and schmoo
HBM2 PHY benefits include:
- Fully hardened 7nm HBM2 PHY for easy integration
- Production-ready design available for licensing: first 7nm product already taped out
- Fifth generation of HBM PHYs proven in silicon
- Interposer design available for faster time to market
- Maximum data rate supported across all timing corners
- HBM2E at 3.2Gbps in development
- Full productization support available: signal integrity, power integrity and thermal analysis
The 56G SerDes and HBM2 PHY are part of eSilicon’s complete, highly configurable, FinFET-class 7nm networking IP platform.