Events
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SemIsrael Expo 2017

November 28, 2017 | Airport City, Israel

SemIsrael Expo 2017 brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 1,000 semiconductor professionals from the Israeli semiconductor community: local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.

Participation (booth area, technical tracks) is free, but requires early registration and approval. SemIsrael Expo provides free entrance, free lunch and free parking to its guests.
There are four tracks that run in parallel throughout the day:

  • IP & Cores
  • Front End & Verification
  • Physical Design
  • Post Silicon

In addition, there will be a 50-booth exhibition area where IP, tools and services will be introduced.

eSilicon at SemIsrael

Enabling the Expanding Cloud: High-Bandwidth Memory, SerDes and 2.5D Solutions

11:30-11:50 AM
IP & Cores track

eSilicon’s Lisa Minwell will present as part of the IP & Cores track. Join us to learn more about 2.5D/HBM2 packaging & solutions for high-bandwidth applications.

We will also be exhibiting, booth 25. Stop by to learn more about our new 7nm IP platform, including HBM2 PHY, TCAM and long-reach SerDes.

Presentation Abstract
The next generation of high-performance computing, graphics and networking applications have increasing needs for bandwidth. If we look at a traditional ASICs with external memory, the complete system is large with many DRAMs taking up board real estate, affecting performance and power consumption. Performance suffers from increased signal latency and more power is required to drive these signals. There is also significant growth in the number of tracks on the substrate as well as an increase in the number of die, leading to routing congestion.

DRAM technology has not been scaling to keep up with this need.  The answer is moving to a stacked memory solution – high-bandwidth memory (HBM). This memory has been defined as a JEDEC standard, JESD235A, and began production in 2015. The use of HBM requires 2.5D packaging with silicon interposer and through-silicon vias.

2.5D technology offers a tremendous increase in capacity and performance. Increased capacity because of the stacked memory in a smaller area and increased performance because of the interposer and shorter signal routing. The interposer allows the integration of highly parallel connections to the memory stacks inside the package, therefore it is able to offer huge capacity and performance increases.