Events
Semisrael Expo 2018

SemIsrael Expo 2018

November 27, 2018 | Airport City, Israel

SemIsrael Expo 2018 brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 1,000 semiconductor professionals from the Israeli semiconductor community: local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.

eSilicon at SemIsrael

7nm 56G DSP SerDes Demonstrations: Booth 42

Using Samtec ExaMAX® Backplane Connector paddle cards and an ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes. Error-free operation (without the need for forward error correction) will be showcased across multiple channels, operation frequencies and modulation schemes, thanks to a very powerful and programmable real-time DSP-based equalization capability. Bit-error rate, eye diagram monitors and pulse response processing will be shown among many other capabilities.

An IP Platform for High-Performance Networking ASICs

Meeting the power, performance and density requirements of advanced networking-class ASICs is a significant challenge for system OEMs. Next-generation 12.8, 25.6 and 51.2 Tb/s switches and routers demand extreme flexibility in system architecture, I/O bandwidth and memory subsystems to achieve the required performance at a commercially acceptable power and density. eSilicon’s 7nm IP platform delivers a complete ecosystem of networking-optimized IP with high configurability designed in. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.

The platform includes high-performance, extremely flexible 56G and 112G SerDes, a ternary CAM (TCAM) compiler, a robust and programmable high-bandwidth memory (HBM2) PHY, multiple network-optimized memory compilers and extended-voltage general-purpose and LVDS I/O libraries.

Presented on the IP & Cores Track by David Axelrad, Senior Director, IP Marketing, eSilicon

An IP Platform for AI ASICs

AI ASICs are typically challenged by changing AI algorithms that are difficult for a static ASIC design to adapt to. Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, the neuASIC™ AI ASIC IP platform removes the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators.

The neuASIC IP platform has been through several 7nm tapeouts. The platform includes an array of compiled, hardened and verified functions and also provides a software AI accelerator builder function that provides power/performance/area (PPA) estimates of the chosen ASIC architecture before RTL development starts.

Presented on the AI & Machine Learning Track by Pierre Boyer, Sales and Applications Manager, eSilicon

SemIsrael Details

Participation (booth area, technical tracks) is free, but requires early registration and approval. SemIsrael Expo provides free entrance, free lunch and free parking to its guests.
There are four tracks that run in parallel throughout the day:

  • AI & Machine Learning Track
  • IP & Cores
  • Front End & Verification
  • Physical Design
  • Post Silicon

In addition, there will be a 50-booth exhibition area where IP, tools and services will be introduced.