Press Release

eSilicon at DAC 2017

2.5D/HBM2 FinFET ASIC & IP Solutions for High-Bandwidth Networking, Computing, AI and 5G Infrastructure

For release on June 13, 2017, San Jose, Calif.

eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, will participate at several venues at the 2017 Design Automation Conference (DAC) in Austin, Texas at the Austin Convention Center, June 18-22, 2017.

Heart of Technology (HOT) Party DAC 2017 logo eSilicon is proud to be a sponsor of the Heart of Technology (HOT) Party at DAC 2017
Who: DAC attendees, sponsors
What: Charity benefit party at DAC—Gary Smith Foundation Scholarship at San Jose State University
Where: Speakeasy Austin, 412 Congress Ave, Austin, TX (downtown, walk from DAC location)
When: Monday, June 19, 7:00pm – 11:00am
Samsung Open Collaboration Theater
Enabling the Connected Planet with eSilicon’s 14LPP IP Platform

Lisa Minwell, eSilicon’s senior director, IP marketing, will discuss real-world high-performance applications of our silicon-verified 14LPP IP platform.

  • Monday, June 19, 4:45 PM
  • Wednesday, June 21, 4:45 PM

SOC Theater, Samsung Booth 921

ChipEstimate.com IPTalks! logo ChipEstimate IP Talks!
FinFET ASICs: Fueling the Cloud

eSilicon provides advanced FinFET ASICs to system OEMs in the high-bandwidth networking, high-performance computing, artificial intelligence (AI) & 5G wireless infrastructure markets through an open, collaborative model with sophisticated automation and differentiated IP. The presentation will share examples of FinFET ASICs, showcasing highly differentiated IP and 2.5D solutions. Presenter: Lisa Minwell, eSilicon’s senior director of IP marketing.

  • Monday, June 19, 2:00 PM
  • Tuesday, June 20, 11:00 AM
  • Wednesday, June 21, 2:30 PM

ChipEstimate.com Booth 347

Mentor, a Siemens Business logo Achieving Best PPA and Fast Turnaround Using Oasys-RTL Design Space Exploration Technology

eSilicon will share its experiences in deploying Oasys-RTL design space exploration capabilities for logic and memory optimization on their advanced SoC designs. Design space exploration (DSE) helps explore various design alternatives during RTL synthesis and pick the best configuration for implementation. The session will use case studies and data points to discuss how Mentor’s solutions were able to improve productivity and shorten design cycle times.

eSilicon presenter: Prasad Subramaniam, VP R&D and design technology.

  • Tuesday, June 20, 3:00-4:00PM

Mentor Booth 947

Visit the Design Automation Conference 2017 website for the latest information.

About eSilicon
eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.

www.esilicon.com
Collaborate. Differentiate. Win.™

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eSilicon is a registered trademark, and the eSilicon logo and Collaborate. Differentiate. Win. are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

Sally Slemons
eSilicon Corporation
408.635.6409
sslemons@esilicon.com

Susan Cain
Cain Communications
408.393.4794
scain@caincom.com