Press Release

eSilicon to present Mastering SI/PI for Advanced Package Design at the ANSYS Innovation Conference, Santa Clara, California

eSilicon, an independent provider of FinFET-class ASIC design, market-specific IP platforms and advanced 2.5D packaging solutions, will present Mastering SI/PI for Advanced Package Design at the ANSYS Innovation Conference, August 2, 2018, in Santa Clara, California.

What:
Mastering SI/PI for Advanced Package Design
ASIC packaging becomes more complex with increasing density, faster data rates and higher power. Verifying a package design requires chip-package-system co-analysis for signal integrity (SI) and power integrity (PI). The ANSYS HFSS, SIwave and RedHawk tools are integrated into the eSilicon SI/PI workflow for advanced package design. This presentation is a technical overview of this SI/PI design process and workflow.

Who:
Teddy Lee, Architect, Signal Integrity & Power Integrity, eSilicon Corporation

When:
Thursday, August 2, 2018
11:45 AM-12:15 PM

Where:
Hyatt Regency, Santa Clara, California

About the ANSYS Innovation Conference
Attend the ANSYS Innovation Conference to learn more about what sets ANSYS software apart from other engineering simulation tools. Presenting customers and ANSYS technical experts will discuss how a consolidated simulation platform enables engineering teams throughout the entire supply chain to confidently address increasing system complexity and successfully meet product targets (launch date, cost, quality) while significantly reducing the total cost of ownership of engineering simulation tools.

This one-day conference brings together ANSYS technology users, partners, developers, and industry experts for networking, learning and sharing of innovative ideas.

Diagram: example voltage drop plot from the DC power integrity analysis

Example voltage drop plot from DC power integrity analysis

About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com

Collaborate. Differentiate. Win.™

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eSilicon is a registered trademark, and the eSilicon logo and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

Sally Slemons
eSilicon Corporation
408.635.6409
sslemons@esilicon.com

Susan Cain
Cain Communications
408.393.4794
scain@caincom.com