eSilicon Announces Availability of neuASIC IP Platform for AI ASIC Design
Validated 7nm platform includes 56G SerDes, HBM2 PHY, AI mega/giga cells, including convolution engine and accelerator builder software
SAN JOSE, Calif. — September 18, 2018 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the availability of its 7nm neuASICä IP platform for customer AI ASIC designs. AI ASICs are typically challenged by changing AI algorithms that are difficult for a static ASIC design to adapt to. Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, the neuASIC platform removes the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators.
“Effective ASIC design for AI accelerators requires a holistic view of the problem, from effectiveness of the architecture to energy efficient implementation of application-specific parallelism,” said Dr. Dileep Bhandarkar, an independent neural network consultant and former vice president of technology at Qualcomm Datacenter Technologies. “The eSilicon neuASIC platform provides system architects with verified customizable IP building blocks that can reduce time to market. The availability of a high-performance SerDes opens up additional options for the system designer.”
“Our goal with the neuASIC platform was to allow faster, more energy efficient AI ASIC design that was adaptable to changing algorithm requirements,” said Patrick Soheili, vice president, business and corporate development at eSilicon. “I am confident the current IP platform will achieve this goal. Our extensive custom memory design capability has been a key enabler to deliver the required functionality.”
The neuASIC IP platform has been through several 7nm tapeouts. The platform includes the following compiled, hardened and verified functions:
- Configurable multiply-accumulate (MAC) blocks
- Single-port SRAM
- Pseudo two-port and pseudo four-port SRAM
- Ternary content-addressable memory (TCAM)
- Pitch match memory
- GIGA memory
- WAZPS (word all zero power saving) memory
- Transpose memory
- Re-mapper – low power cross-bar
- Convolution engine
- 56G SerDes
- HBM2 PHY
The platform also provides a software AI accelerator builder function that provides power/performance/area (PPA) estimates of the chosen ASIC architecture before RTL development starts.
To learn more about eSilicon’s 7nm neuASIC IP platform or to inquire about access to the platform for design, visit eSilicon’s neuASIC web page or contact your eSilicon sales representative directly or via email@example.com.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
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