eSilicon Announces Production Qualification of 5G Infrastructure ASIC
Collaborative effort with ASE, Rambus, Samsung and UMC to build large, 2.5D FinFET design
SAN JOSE, Calif. — May 14, 2019— eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today that a large 2.5D FinFET ASIC targeting the 5G infrastructure market is entering final product qualification. The design, which is over 600mm2, contains multiple HBM2 memory stacks on a silicon interposer, employs over 100 lanes of SerDes and contains over 800Mb of embedded SRAM.
The design was a collaboration of several ecosystem partners, including ASE for the advanced package, Rambus for the high-performance SerDes, Samsung for the 14nm FinFET ASIC fabrication and HBM memory stacks and UMC for the silicon interposer.
“Designs of this size require specialized analysis and materials, so collaboration between ecosystem players has become more crucial than ever,” said Calvin Cheung, VP of engineering at ASE Group. “ASE is pleased to have played a key role in bringing such a large and challenging design to production.”
“Rambus’ high performance and flexible SerDes technology, with a large number of SerDes lanes running at various speeds, is a key enabler for this complex ASIC,” said Hemant Dhulla, VP and GM of IP Cores at Rambus. “We are excited to collaborate with our ecosystem partners on the strategic elements to drive the next-generation 5G network growth.”
“This is one of the largest dies we have produced in this 14nm node,” said Hong Hao, SVP of Foundry Sales and Marketing at Samsung Semiconductor, Inc. “We are delighted to see this design successfully entering the production phase.”
“Our advanced HBM2 technology is enabling many innovative designs such as eSilicon’s collaborative advancement here,” said Pablo Temprano, VP of Memory Marketing, Samsung Semiconductor, Inc. “The 5G market will mark a new era of technological efficiency for which this 2.5D FinFET ASIC is set to help lead the way.”
“Many 5G designs will require 2.5D technology with a silicon interposer,” said Walter Ng, VP of sales at UMC. “UMC’s technology provides a critical enabler for these designs.”
“It is gratifying to see a design this complex move through qualification so quickly,” said Ajay Lalwani, VP of Global Manufacturing Operations at eSilicon. “Getting this design into production was a real team effort between eSilicon and our ecosystem partners. This teamwork, and the resultant success of this complex part in the end system is the new definition of ASIC success.”
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
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