Interoperability demo at OFC: eSilicon 56G SerDes and Precise-ITC 400G FEC
Interoperability demonstrated between eSilicon 7nm SerDes and Intel Stratix 10 FPGA
SAN DIEGO, Calif. — March 5, 2018 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today at the OFC conference in San Diego an interoperability demonstration in their booth #5416. The demonstration verifies interoperability between eSilicon’s 56G PAM4 & NRZ DSP-based long-reach 7nm SerDes and the SerDes embedded in an Intel® Stratix® 10 FPGA. 400Gb/s Forward Error Correction (FEC) for the demo is implemented with the Precise-ITC E-pak 400G core instantiated in the Intel Stratix 10 FPGA.
The demonstration will show loop-back testing between the Intel Stratix 10 FPGA and the eSilicon SerDes running at 53.125Gb/s in PAM4. The capabilities of the Precise-ITC 400GE PCS and MAC with KP4 FEC will also be demonstrated. The Precise-ITC Ethernet packet generator and monitor in the FPGA are used to generate full rate 400Gb/s traffic. Per-lane FEC statistics and packet statistics are collected and displayed through the attached PC with the PreciseTalk© GUI to show SerDes performance and error rate.
Additional features of the demo include:
- Demonstration of Precise-ITC’s FEC performance, dynamic skew adjustment and automatic lane reordering at the 400GE PCS
- Demonstration of Precise-ITC’s feature-rich PCS, comprehensive FEC and MAC statistics implemented in an Intel Stratix 10 FPGA
This demo will be added to the compliment of demos currently running in the eSilicon booth at OFC, which include:
- A demonstration highlighting the performance, flexibility and extremely low power consumption of eSilicon’s 7nm SerDes using Samtec ExaMAX® Backplane Connector paddle cards and a five-meter ExaMAX Backplane Cable Assembly. This demonstration will span two demo pods and will feature eight high-speed SerDes lanes operating with two different modulation schemes and multiple bit rates
- A demonstration featuring a complete high-bandwidth memory Gen2 (HBM2) solution in 7nm operating at 2.4Gbps. This demonstration includes eSilicon’s latest 7nm HBM2 PHY, Northwest Logic’s memory controller and an HBM DRAM stack from a leading memory supplier
“Our current SerDes demonstration showcases the robustness, low power and flexibility of our 7nm device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “It is also important to demonstrate interoperability with other popular hardware. I am delighted we can showcase this additional aspect of our SerDes capabilities at OFC.”
“Precise-ITC is a leading provider of Ethernet and optical transport (OTN) intellectual property products for ASIC and FPGA,” said Silas Li, Director of Engineering at Precise-ITC. “OFC2019 is a showcase event for the partnerships we have with FPGA vendors, ASIC developers, like eSilicon, and test equipment developers. Together, we’re enabling rapid deployment of 400GbE.”
eSilicon will be demonstrating its advanced SerDes technology and HBM2 PHY at OFC2019 in booth #5416. Precise-ITC will be demonstrating its standards-compliant 400G Ethernet core with the Spirent tester at OFC2019 in booth #6208.
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
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