eSilicon to present “Demystifying 2.5D ASIC Production” at 3D ASIP 2016
How to navigate the complex HBM/2.5D ecosystem, plus what’s next for multi-chip integration
For release on Dec 6, 2016, San Jose, Calif. – eSilicon, a leading semiconductor design and manufacturing solutions provider, will present at the 2016 3D Architectures for Semiconductor Integration and Packaging (ASIP) Conference held in San Francisco, California, December 13-15, 2016.
Session 3: Memory Stacks and Applications
eSilicon will describe how it manages a complex HBM/2.5D ecosystem of suppliers and advanced technologies — such as high-bandwidth memory (HBM) and high-bandwidth interconnect (HBI) — for tier-one customers demanding very high-performance chips.
Patrick Soheili, eSilicon’s VP, product management and corporate development, will present Demystifying 2.5D ASIC Production.
Tuesday, December 13, 2016 4:40-5:00 PM
Marriott San Francisco Airport Waterfront
1800 Old Bayshore Highway Burlingame, CA 94010
About 3D ASIP
3D ASIP is recognized as the premier conference on 2.5/3D IC focused on commercialization and infrastructure. Continuing the tradition of offering cutting-edge presentations from scientists, technologists and business leaders from across the globe. For more information, visit the 3D ASIP conference website.
eSilicon guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the automotive, communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results. www.esilicon.com
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