7nm High-Bandwidth Interconnect PHY for Die-to-Die Interconnects

Enabling Highly Complex Next-Generation ASICs & SoCs

Next-Gen ASIC & SoC Challenges

Key challenges facing complex chip architects:

  • The number of gates and memories is approaching multiple billions
  • Die size can exceed 500 square millimeters
  • Silicon yield is a key factor in solution cost; partitioning is an architectural approach to the optimal solution

HBI+ Interconnect PHY Joins Our Plug-and-Play 7nm IP Platform

The high-bandwidth interconnect (HBI™)+ PHY is part of eSilicon’s 7nm IP platform — a complete ecosystem of highly configurable IP, optimized for networking, data center and AI. All of the IP in the platform are “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility result in better performance, higher density and faster time to market.

eSilicon’s HBI+ PHY deliverables are available now for customer ASIC and SoC designs.  

Enabling Next-Gen Complex ASICs & SoCs for Networking, Data Center and AI Systems

eSilicon’s HBI+ technology delivers a new level of die-to-die interconnect PHY. It is a high-bandwidth, low-power, low-latency multi-channel PHY intended for interconnecting multiple die mounted within a package.

It is a wide DDR interface utilizing a clock-forwarded bus architecture that takes advantage of packaging innovations that offer much finer pitch die-to-die connections than traditional flip-chip organic substrates. Examples include TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) or other silicon interposer technologies and other fine-pitched die-to-die interconnect technologies. 

The HBI+ PHY can be used in applications requiring high-bandwidth, low-latency connections between die within a package: 

  • Connecting an SoC to a smaller chiplet containing multiple lanes of SerDes or other functions to implement the SoC in a different process node or foundry than that of the IP in the chiplet
  • Partitioning a large SoC into multiple smaller SoCs for flexibility in configuration or for improving yield 
  • Enabling multiple SoCs to be packaged together to create complex subsystems
High-bandwidth interconnect PHY diagram
HBI+ interconnect PHY enables the use of chiplets to leverage proven technology


large ASIC to multiple ASICs

ASIC cost savings with multiple die vs. monolithic die
Managing ASIC cost and yield through “divide and conquer”


Unique Benefits & Features of eSilicon’s 7nm HBI+ PHY Family

True High-Bandwidth Die-To-Die Interconnect PHY with up to
2 Tbps/mm of Die Edge (1Tbps/mm in Each Direction) 

  • Data rate: 7nm HBI+ PHY delivers up to 4Gbps per pin
  • AIB Plus compliant: Intel Advanced Interface Bus (AIB) version 1.1

Easy to Use and to Integrate

  • Self-contained hard macro, fully timing closed
  • Self-calibrating Rx sampling phase and threshold selection 
  • Built-in self-test (BIST), internal loopback and external PHY-to-PHY link test
  • IEEE 1149.1 (JTAG) boundary scan

Flexible & Programmable 

  • Flexible configuration: up to 160 pins (80 Rxs and 80 Txs) per channel and up to 24 channels per PHY
  • EW (east, west) orientation, NS (north, south) possible
High-Bandwidth Interconnect (HBI) PHY Block Diagram
Example HBI+ PHY implementation of die-to-die interconnect


More Information

Additional details are available under NDA. Contact your eSilicon sales representative directly or via sales@esilicon.com.