Cloud, data center, networking and AI applications are resulting in an explosion of data being generated, moved, stored and analyzed. Building ASICs that support the massive need for memory and processing requires working in advanced FinFET-class solutions such as high-bandwidth memory (HBM2) stacks, 2.5D packaging and IP optimized specifically for high-performance, high-bandwidth markets. It requires doing things in silicon that have never been done before.
eSilicon specializes in high-performance, high-bandwidth IP + 2.5D solutions that target networking, high-performance computing and artificial intelligence (AI) applications. eSilicon’s specialized IP ecosystem in this category includes a high-performance, extremely configurable 58G and 112G SerDes family; a ternary content-addressable (TCAM) compiler; a configurable, high-bandwidth memory (HBM2) PHY, multiple network-optimized memories; and extended-voltage general-purpose and LVDS I/Os.
eSilicon’s 7nm IP platform delivers a complete ecosystem of networking-optimized IP with high configurability designed in. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.
This is our second-generation platform with architectural enhancements from our silicon-proven platform in previous FinFET technologies. It was designed specifically to meet the high-speed, high-bandwidth requirements of ASICs and ASSPs targeted for networking and high-performance computing applications.
Additional features and benefits for eSilicon’s 7nm IP platform are available under NDA. Contact firstname.lastname@example.org. Front-end views of our 7nm IP offering are available now by contacting email@example.com.
Our silicon-proven 14/16nm specialized memories provide 2.5GHz worst-case operation with more than a billion searches per second along with the 2.5D integration of 1024 Gbytes/sec data rate high-bandwidth memory (HBM2).
At the core of our 7nm IP platform is eSilicon’s SerDes technology, a new breed of performance and versatility based on a novel DSP-based architecture. Two 7nm PHYs support 58G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The architecture delivers unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1 Gb/s. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including Ethernet and Fibre Channel. The architecture allows scaling power consumption even further for shorter-reach channels.
HBM2 achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, or GDDR5. At 14/16nm, HBM2 addresses the bandwidth gap with up to 256GB/s data rate per memory at 2Gbps pin speed.
At 7nm, the pin speed increases to 3.2Gbps and addresses the bandwidth gap with up to 1638 Gbytes/sec data rate with four HBM2 stacks in a package.
The HBM2E PHY interface features eight independent channels using a total of 1024 data pins. With support for 2, 4, or 8 HBM2 stacks, the density of signals, coupled with interposer design, requires careful design, thorough timing analysis and validation. eSilicon’s HBM2 PHY is a complete, validated hardened IP that is ready for chip integration.
eSilicon’s 2.5D/HBM2 is first to production with a comprehensive 2.5D solution that includes eSilicon’s HBM2 PHY, interposer and systems in package (SiP) design; volume manufacturing, assembly and test; and complete 2.5D/HBM ecosystem management.
Memory processing tends to be the bottleneck in network performance. If memory cannot keep up with increasingly fast processors, the processors have to wait, stalling the system. Specialty memories address the problem in a variety of ways. Ternary content-addressable memories (TCAMs) are unique ─ they search an entire lookup table in one cycle. eSilicon’s 7nm ternary CAM compiler provides more than a 50% increase in performance compared to previous FinFET generations, enabling high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.
eSilicon has designed custom high-speed single-port cache memories that are optimized to meet the high-performance requirements of industry-standard processor cores. Our 14LPP high-speed single-port fast cache compiler is part of our complete 14LPP IP platform. eSilicon’s new 7nm fast cache compiler offers more than a 35 percent increase in performance from previous FinFET generations.
eSilicon has designed four-port register file memory compilers and asynchronous register file memory compilers catering to multiple customers in the networking and communications domains. The four-port memories have two write ports and two read ports. The asynchronous memories have one synchronous write port and one asynchronous read port.
eSilicon’s HBI+ technology delivers a new level of die-to-die interconnect PHY. It is a high-bandwidth, low-power, low-latency multi-channel PHY intended for interconnecting multiple die mounted within a package.
It is a wide DDR interface utilizing a clock-forwarded bus architecture that takes advantage of packaging innovations that offer much finer-pitch die-to-die connections than traditional flip-chip organic substrates.
|High-speed SP TCAM|
|Ultra-high-speed SP TCAM|
|High-speed SP fast cache|
|High-speed DP SRAM|
|High-speed pseudo 2-port SRAM|
|High-density pseudo 2-port SRAM|
|High-density 2-port asynchronous RF|
|Ultra-high-speed pseudo 2-port SRAM|
|High-speed four-port register file|
|1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library|
|1.8V oxide 1.8V LVDSOUT I/O library|
|1024-bit HBM2 PHY|
|58G long-reach SerDes|
|112G long-reach SerDes|
|High-speed single-port ternary CAM (SP TCAM) compiler|
|High-speed single-port fast cache (FC) compiler|
|High-speed single-port (SP) SRAM compiler|
|High-density single-port (SP) SRAM compiler|
|High-speed dual-port (DP) SRAM compiler|
|High-speed two-port asynchronous register file (2PARF) compiler|
|High-speed two-port register file (2PRF) compiler|
|High-speed pseudo two-port (P2P) SRAM compiler|
|Ultra-high-density (UHD) pseudo two-port (P2P) SRAM compiler|
|High-speed pseudo four-port (P4P) SRAM compiler|
|High-density two-port asynchronous register file (2PARF) 1R1W latch-base compiler|
|High-density three-port asynchronous register file (3PARF) 2R1W latch-base compiler|
|HBM2/HBM2E/LL HBM PHY|
|High-bandwidth interconnect (HBI™) + PHY for die-to-die interconnects|
|1.8V oxide 1.8V LVDS I/O library|
|1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library|
Front-end views, silicon quality results, white papers or complete data sheets, are available from firstname.lastname@example.org. Additional features and benefits for eSilicon’s 7nm IP platform are available under NDA. Contact email@example.com.
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.