FinFET-Class 7nm IP Platform

New Architectures Support High Bandwidth, High Density, Lower Power

eSilicon offers a set of high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target networking and high-performance computing applications by offering 3.3GHz caches and TCAMs with up to 1.8 billion searches per second (worst-case operation), along with the 2.5D integration of up to 1228 Gbytes/sec data rate high-bandwidth memory (HBM2).

7nm High-Bandwidth Networking & High-Performance Computing IP Platform

The 7nm IP platform is eSilicon’s second-generation platform, with architectural enhancements from our silicon-proven platform in previous FinFET technologies. It was designed specifically to meet the high-speed and high-bandwidth requirements of ASICs and ASSPs targeted for networking and high-performance computing applications. The platform includes the following IP:

  • 56G long-reach SerDes
  • High-speed single-port ternary CAM (SP TCAM) compiler
  • High-speed single-port fast cache (FC) compiler
  • High-speed single-port (SP) SRAM compiler
  • High-speed dual-port (DP) SRAM compiler
  • High-speed 2-port asynchronous register file (2PARF) compiler
  • High-speed pseudo 2-port (P2P) SRAM compiler
  • Ultra-high-density (UHD) pseudo 2-port (P2P) SRAM compiler
  • High-speed pseudo 4-port (P4P) SRAM compiler
  • High-speed pseudo quad-port (PQP) SRAM compiler
  • High-speed single-port ternary CAM (SP TCAM) compiler
  • 1024 bit HBM2 PHY
  • 1.8V oxide 1.8V LVDS I/O library
  • 1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library

Highlights of the New Architectures

Optimized for Performance

  • Except for the UHD P2P SRAM, all memory compilers in the 7nm IP platform are optimized for performance, offering speeds in access of 1.8GHz and >2.0GHz for smaller instances, under worst case operating conditions with overdrive voltage
  • High-speed fast cache compiler offers speeds up to 3.3GHz
  • High-speed P2P SRAM compiler is expected to run at 1.8GHz, while providing high density for two-port functionality

Optimized for Bandwidth, Density & Power

  • The high-speed pseudo four-port and pseudo quad-port SRAM are new architectures introduced in 7nm to support parallel operations to increase system bandwidth. The PQP allows up to four simultaneous read or write operations. The P4P and PQP provide high bandwidth with the best density and power savings for critical applications requiring multi-port architectures.
  • For applications requiring lower clock speeds (600-900MHz), the ultra-high-density pseudo two-port SRAM compiler provides extreme area savings and reduction in dynamic and leakage power by up to 40 and 70 percent, respectively.

Why TCAM?

Memory processing tends to be the bottleneck in network performance. If memory can’t keep up with increasingly fast processors, the processors have to wait, stalling the system. Specialty memories address the problem in a variety of ways. Ternary content-addressable memories (TCAMs) are unique: they search an entire lookup table in one cycle. eSilicon’s eFlexCAM™ TCAM compiler provides up to 2.5 billion search results in one second (GSPS) under typical operating conditions, enabling high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.

TCAM Standard Features

  • Flexible selection of width and depth: compiler-based with up to 160Kb
  • Up to 1K entries and up to 160 bits per word
  • Hand-crafted layout for high density and performance
  • Easily cascadable to increase search depth without degradation in performance
  • Single-cycle search, read and write operations
  • Smart Power Management
  • Fast cycle and access time: 1.8 GSPS worst case and up to 2.5 GSPS under typical conditions
  • Valid bit, global and local valid-bit reset
  • Match-in and match-out flag for each entry
  • Partial pipelined search option for reduced power
  • Flexible masking (bit/group/global)

User-selectable features include priority encoder, redundancy and bit-write options.

Patented Duo architecture may be licensed for reduced area and power savings for bit widths less than or equal to 80 bits.

High-Bandwidth Memory

High-bandwidth memory (HBM2) achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, or GDDR5. HBM2 technology addresses the bandwidth gap with up to 1228 Gbytes/sec data rate with four HBM2 stacks in a package. HBM2 has eight independent channels using a total of 1024 input and output pins. This density of signals, coupled with interposer design, requires careful design and thorough timing analysis. eSilicon has extensive experience in HBM2 systems, including IP design, systems in package (SiP) design, manufacturing, assembly and test.

HBM2 PHY

The HBM2 PHY supports HBM2 based on the JEDEC JESD 235A standard. The PHY supports up to 307Gbytes/sec bandwidth with 8x128b channels at 2.4Gbps per I/O. The PHY is DFI 4.0 compliant with several controller-independent features such as:

  • Plug & play: with hard macro and built-in clock control there’s no lengthy timing closure and physical design
  • Optimized timing and area
  • Rich set of built-in features
  • Flexible: minimum dependence on controller features
  • Signal integrity: proprietary routing scheme used on interposer to significantly minimize crosstalk and skew
  • Maximum timing margin: PHY includes training, calibration and VREF programmability features
  • DFI and IEEE1500 compliant
  • APB interface enables CPU override of built-in training, repair and calibration

About eSilicon Memory IP

eSilicon’s 7nm memories provide system-on-chip (SoC) architects with a reliable, affordable method of optimizing their product design. eSilicon optimizes its networking-centric memory compilers by leveraging ASIC system-level requirements for high bandwidth for optimal power, performance or area.

Our IP team has been a leading provider of high-quality memory IP since 2000. Our memories are available in 7nm-250nm technologies, optimized to meet challenging PPA requirements for leading foundry and integrated device manufacturer (IDM) processes.

Contact & Online Access

Please contact eSilicon at sales@esilicon.com for more information, silicon quality results, white papers or data sheets.

All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.

Resources

Our HBM2 webinars and white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, are available at our Start Your HBM2/2.5D Design Today web page.

You may also be interested in our Advanced ASIC Video Series:

  • What is High-Bandwidth Memory (HBM2) and 2.5D Packaging?
  • What is a TCAM?
  • Where is a TCAM Used in an ASIC?