Highly Configurable FinFET-Class 7nm Networking IP Platform

New Architectures Deliver Unprecedented Performance, Density and Configurability

eSilicon offers a set of high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target networking and data center applications by offering 58G/112G SerDes, fast caches with more than a 35 percent increase in performance and TCAMs offering more than a 50 percent increase in performance from previous FinFET generations, along with the 2.5D integration of up to 1638Gbytes/sec data rate high-bandwidth memory (HBM2E).

eSilicon’s second-generation, 7nm networking IP platform was designed for networking and hyperscale data center ASICs image
Example of a hyperscale data center ASIC

7nm High-Bandwidth Networking & High-Performance Computing IP Platform

The 7nm IP platform is eSilicon’s second-generation platform, with architectural enhancements from our silicon-proven platform in previous FinFET technologies. It was designed specifically to meet the high-speed and high-bandwidth requirements of ASICs and ASSPs targeted for networking and data center applications.

eSilicon’s 7nm IP platform delivers a complete ecosystem of networking-optimized IP with high configurability designed in. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.

The platform includes the following IP:

  • 58G long-reach SerDes
  • 112G long-reach SerDes
  • High-speed single-port ternary CAM (SP TCAM) compiler
  • High-speed single-port fast cache (FC) compiler
  • High-speed single-port (SP) SRAM compiler
  • High-density single-port (SP) SRAM compiler
  • High-speed dual-port (DP) SRAM compiler
  • High-speed two-port asynchronous register file (2PARF) compiler
  • High-speed two-port register file (2PRF) compiler
  • High-speed pseudo two-port (P2P) SRAM compiler
  • Ultra-high-density (UHD) pseudo two-port (P2P) SRAM compiler
  • High-speed pseudo four-port (P4P) SRAM compiler
  • High-density two-port asynchronous register file (2PARF) 1R1W latch-base compiler
  • High-density three-port asynchronous register file (3PARF) 2R1W latch-base compiler
  • High-bandwidth interconnect (HBI™) + PHY for die-to-die interconnects
  • 1.8V oxide 1.8V LVDS I/O library
  • 1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library

Highlights of the New Architectures

Optimized for Performance

  • Except for the UHD P2P SRAM, all memory compilers in the 7nm IP platform are optimized for performance, offering a greater than 35 percent increase in performance from previous FinFET generations
  • High-speed fast cache compiler offers extreme speeds suitable for compute-intensive applications
  • High-speed P2P SRAM compiler is expected to run at increased performance while providing high density for two-port functionality

Optimized for Bandwidth, Density & Power

  • The high-speed pseudo four-port SRAM is a new architecture introduced in 7nm to support parallel operations to increase system bandwidth. The P4P provides high bandwidth with the best density and power savings for critical applications requiring multi-port architectures.
  • For applications requiring lower clock speeds, the ultra-high-density pseudo two-port SRAM compiler provides extreme area savings and reduction in dynamic and leakage power by up to 40 and 70 percent, respectively.

Detailed Information

Check out our IP Platforms blog for updates on SerDes and other IP. Additional features and benefits for eSilicon’s 7nm IP platform are available under NDA. Contact sales@esilicon.com.

58G/112G 7nm SerDes

At the core of the platform is eSilicon’s SerDes technology, a new breed of performance and versatility based on a novel DSP-based architecture. Two 7nm PHYs support 58G and 112G NRZ/PAM4 operation to provide the best power efficiency tradeoffs for server, fabric and line-card applications. The architecture delivers unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1 Gb/s. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including Ethernet and Fibre Channel. The architecture allows scaling power consumption even further for shorter-reach channels.

Check out our IP Platforms blog for SerDes updates.

Ternary CAM Unlocks Memory Processing Bottlenecks

Memory processing tends to be the bottleneck in network performance. If memory can’t keep up with increasingly fast processors, the processors have to wait, stalling the system. Specialty memories address the problem in a variety of ways. Ternary content-addressable memories (TCAMs) are unique: they search an entire lookup table in one cycle. eSilicon’s ternary CAM compiler offers more than a 50 percent increase in performance, compared to previous FinFET generations, enabling high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.

TCAM Standard Features

  • Flexible selection of width and depth with up to 1K entries and 160Kb macro size
  • Hand-crafted layout for high density and performance
  • Easily cascadable to increase search depth without degradation in performance
  • Single-cycle search, read and write operations
  • Smart Power Management
  • Fast cycle and access time: the 7nm TCAM offers more than a 50 percent increase in performance
  • Valid bit, global and local valid-bit reset
  • Match-in and match-out flag for each entry
  • Partial pipelined search option for reduced power
  • Flexible masking (bit/group/global)

User-selectable features include priority encoder, redundancy and bit-write options.

Patented Duo architecture may be licensed for reduced area and power savings for bit widths less than or equal to 80 bits.

High-Bandwidth Memory

HBM2E achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, GDDR5 or hybrid memory cube (HMC). HBM2E technology addresses the bandwidth gap with up to 1638Gbytes/sec data rate with four HBM2E stacks in a package. HBM2E has eight independent channels using a total of 1024 input and output pins. This density of signals, coupled with interposer design, requires careful design and thorough timing analysis. eSilicon has extensive experience in HBM2 and HBM2E systems, including IP design, systems in package (SiP) design, manufacturing, assembly and test.


The HBM2E PHY supports HBM2 and HBM2E based on the JEDEC JESD 235A and JESD 235B standards. The PHY supports up to 409.6Gbytes/sec bandwidth with 8x128b channels at 3.2Gbps per I/O. The PHY is DFI 4.0 compliant with several controller-independent features such as:

  • Plug & play: with hard macro and built-in clock control there’s no lengthy timing closure and physical design
  • Optimized timing and area
  • Rich set of built-in features
  • Flexible: minimum dependence on controller features
  • Signal integrity: proprietary routing scheme used on interposer to significantly minimize crosstalk and skew
  • Maximum timing margin: PHY includes training, calibration and VREF programmability features
  • DFI and IEEE1500 compliant
  • APB interface enables CPU override of built-in training, repair and calibration

High-Bandwidth Interconnect PHY for Die-to-Die Interconnects 

eSilicon’s HBI+ technology delivers a new level of die-to-die interconnect PHY. It is a high-bandwidth, low-power, low-latency multi-channel PHY intended for interconnecting multiple die mounted within a package.

It is a wide DDR interface utilizing a clock-forwarded bus architecture that takes advantage of packaging innovations that offer much finer-pitch die-to-die connections than traditional flip-chip organic substrates.

About eSilicon’s 7nm Networking IP Platform

eSilicon’s 7nm memories provide system-on-chip (SoC) architects with a reliable, affordable method of optimizing their product design. eSilicon optimizes its networking-centric memory compilers by leveraging ASIC system-level requirements for high bandwidth for optimal power, performance or area.

Our IP team has been a leading provider of high-quality memory IP since 2000. Our memories are available in 7nm-250nm technologies, optimized to meet challenging PPA requirements for leading foundry and integrated device manufacturer (IDM) processes.

Detailed Information

Front-end views, silicon quality results, white papers or complete data sheets, are available from sales@esilicon.com. Additional features and benefits for eSilicon’s 7nm IP platform are available under NDA. Contact sales@esilicon.com.

Online Access

All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.


White Papers

  • The New Deep Learning Memory Architectures You Should Know About | eSilicon
  • Supercharge Your Applications with Samsung High-Bandwidth Memory | Samsung Memory
  • Multi-Die Packaging and Thermal Superposition Modeling | Amkor, eSilicon & Samsung Foundry for Semitherm 2018
  • Start Your HBM/2.5D Design Today | eSilicon, SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems

Videos & Webinar Replays


  • 7FF IP platform for networking, high-performance computing, AI & 5G
  • 14LPP IP platform for networking, high-performance computing, AI & 5G
  • Ternary CAMs (TCAMs)
  • 28/16/14/7nm HBM2 PHY