Single-Port Register File & Two-Port Register File

Register-File Memory Compilers

eSilicon has designed single-port and two-port register-file memory compilers catering to wide variety of market segments.

Ultra-Low-Voltage and Ultra-Low-Power Register Files for the IoT Spectrum

We are gradually being surrounded by a network of physical objects or “things” embedded with electronics to make them “smart.” These devices are mostly on and listening to incoming data. Therefore, optimizing for very low voltage and power is critical for maintaining long battery life. Internet of Things (IoT) medical and wearables customers benefit from eSilicon’s ultra-low-power and ultra-low-voltage register files for these extreme requirements.

High-Speed Register Files for Networking and Big Data Analytics

IoT is expected to generate large amounts of data from the plethora of “things” from diverse industries and locations, thereby increasing the need for improved performance and bandwidth in networking and communications. Networking and communications customers rely on the performance of eSilicon’s high-speed register files at 40nm, 28nm, 16nm and 14nm to meet the demanding wireline speed requirements of networking applications and the sophisticated cloud-based processing of Big Data.

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Low-Power, High-Performance Register Files for Wireless and Handheld

Wireless and handheld customers engage with eSilicon to develop low-power, high-performance register files that can meet the low battery life requirements of wireless and handheld devices, while at the same time deliver the level of performance required by state-of-the-art devices such as smart phones.

eSilicon’s philosophy for developing memories is to customize the memories to end-customer requirements. This usually involves turning on multiple knobs to tune the area, power, performance of register files per customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.

Area Performance Power Management Testability Functional Options
  • Aspect Ratio
  • Side Decode
  • Push-Rule Bit Cell
  • Low Vt for Highest Performance
  • Banking
  • Center Decode
  • Array Source Biasing
  • Periphery Shutdown
  • Complete Shutdown
  • Dual Rail
  • DVFS
  • Mixed Vt Periphery
  • High Vt Periphery
  • BIST Mux
  • Scan Flops
  • Synchronous Bypass
  • Read Stress
  • Write Stress
  • Column Redundancy
  • Row Redundancy
  • Bit Write
  • Pipelined Output

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Search, select and try eSilicon® IP online at no cost or obligation. Find out more about eSilicon Navigator (formerly IP MarketPlace).