14/16nm Memory IP

Advanced IP for Advanced Technologies:
eSilicon has SRAM, CAM, I/O Libraries & 
HBM PHY on 14/16nm

eSilicon is offering a variety of IP in advanced FinFET and FD-SOI process technologies.

Figure 1: eSilicon IP Development for Advanced Nodes

14/16nm memory IP development timeline at eSilicon

14/16nm Networking and Computing Market-Differentiated IP

eSilicon has developed an IP platform that differentiates networking and computing ASICs and ASSPs with increased performance and bandwidth. The IP platform includes high bandwidth memory (HBM) PHY, extended voltage range general-purpose I/O (EVGPIO) and specialty I/O libraries and eFlex™ SRAMs and register files as shown in the figure below.

Figure 2. 14/16nm eSilicon Differentiating IP

14/16nm memory IP offering from eSilicon

High-Bandwidth Memory PHY

eSilicon has designed IP and systems in package (SiP), manufactured, assembled and tested systems that include HBM. eSilicon’s HBM SoC subsystem is comprised of a hard macro and built-in clock control so there’s no lengthy timing closure and physical design. It includes a rich set of built-in features with minimal dependence on controller features. The PHY includes training, calibration, VREF programmability features, and is DFI and IEEE1500 compliant. A custom routing scheme is used on interposer to significantly minimize crosstalk and skew. The APB interface enables CPU override of built-in training, repair and calibration.

Ternary CAM

eSilicon has silicon-verified eFlexCAM™ ternary content-addressable memories (TCAMs) in one or more of these advanced technologies: 14nm and 16nm FinFET processes.

The TCAM is an excellent choice for packet forwarding and classification in internet routers as well as in a variety of other applications that require high-speed table lookup. eSilicon’s TCAM provides performance of 2.5 billion searches per second (BSPS) under typical operating conditions with overdrive voltage and a latency of 1 clock cycle. TCAM performance is 1.25 giga searches per second (GSPS) under worst operating conditions. Such high-performance, low-latency TCAMs are critical for packet classification at wire speeds. TCAM compilers include features such as hardened priority encoders, multiple options to lower power, and column redundancy for higher yield. TCAM IP includes multi-width search mode to switch dynamically between IPv4 and IPv6 searches. eSilicon also offers built-in self-test (BIST) and built-in self-repair (BISR) for high test coverage during wafer sort and production. Customers may also purchase proprietary TCAM ECC architecture for today’s networking applications.

Pseudo Two-Port SRAM Compiler

There are two pseudo 2-port SRAM compilers: one optimized for high speed running at 1.2GHz worst case and a high density running at 900MHz worst case. The Pseudo SRAM architecture is a high-density, low leakage alternative to traditional SRAMs. Pseudo SRAMs are multi-port memories constructed from regular single or dual port SRAMs. The pseudo SRAM architecture is double clocked internally to achieve multi-port functionality with significant area reduction as a result of incorporating smaller bit cells.

Pseudo multi-port SRAMs with 8-port, 12-port or 16-port functionality can also be constructed using multiple pseudo SRAMs.

High-Speed Cache Compiler

eSilicon’s high-speed cache compiler is targeted to exceed 2.4GHz operation with small setup and hold times on the Address, Data, Bit Write, Memory Enable, and Write Enable input pins at worst case conditions.

Two-Port Asynchronous Register File Compiler

The two-port asynchronous register file compiler offers speeds that exceed 2 GHz under typical operating conditions.

Dual-Port SRAM Compiler

The dual-port SRAM supports two independent read and write ports, and plays a critical role in increasing system bandwidth by supporting parallel operations. These memories provide zero clock latency overhead, deterministic timing (versus RTL/synthesis-based solutions).

Extended-Voltage GPIO Library (1.8V/2.5V/3.3V)

The EVGPIO library contains a set of bi-directional I/O cells and all necessary analog, power-up, power, ground, corner, and filler cells. This library is designed to optimize I/O performance with a nominal core voltage and a wide range of I/O supply voltages: 1.8V, 2.5V and 3.3V (typical case). This library is compliant with industry standard ESD, LU and electrical guidelines.

PPA-Optimized Memory IP

Our memories are optimized across the spectrum of performance, power, area and yield to address customer-specific market requirements. eSilicon memories support industry-standard EDA flows. We work closely with our foundry and integrated device manufacturer (IDM) partners to incorporate the latest guidelines, including statistical analysis, design for manufacturability (DFM) rules, and redundancy guidelines. We collaborate with our customers to customize an already-developed memory compiler or instance and optimize the functionality, performance, power, area or yield to match their SoC’s design-specific needs.


eSilicon’s TCAM compiler, two-port register file compiler, and dual-port SRAM compiler design kits are now available in 14nm and 16nm technologies. Customers can license one or more configurations of TCAM instances generated by the eFlexCAM compiler. Customers can also license the eSilicon register file and dual-port SRAM compilers on a per-project basis. Custom instances to meet customers’ specific performance, power, area and yield targets are also available. For silicon quality report results, data sheets, white papers or information on these new memories, please contact us at ipbu@esilicon.com. eSilicon’s TCAM, two-port register file, and dual-port SRAM are available through the TSMC9000 program.

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