With the increasing number of Internet-connected consumer devices, manufacturing systems, business tools, customer service appliances, medical equipment, agricultural sensors and other devices, the difference between required and available bandwidth will become huge. High-speed, high-bandwidth networking enables the aggregation, automation and analysis of this data.
eSilicon offers high-performance and high-bandwidth IP and 2.5D solutions that target networking and high-performance computing applications by offering 2.5GHz worst-case operation with more than a billion searches per second along with the 2.5D integration of 1024 Gbytes/sec data rate high-bandwidth memory (HBM2).
Figure 1: eSilicon IP Development for Advanced Nodes
eSilicon has developed an IP platform that differentiates networking and computing ASICs and ASSPs with increased performance and bandwidth. The IP platform includes HBM2 PHY, extended-voltage-range general-purpose I/O (EVRGPIO) and specialty I/O libraries, eFlex™ SRAMs and register files.
eSilicon has designed IP and systems in package (SiP), manufactured, assembled and tested systems that include HBM. eSilicon’s HBM SoC subsystem is comprised of a hard macro and built-in clock control so there’s no lengthy timing closure and physical design. It includes a rich set of built-in features with minimal dependence on controller features. The PHY includes training, calibration, VREF programmability features, and is DFI and IEEE1500 compliant. A custom routing scheme is used on interposer to significantly minimize crosstalk and skew. The APB interface enables CPU override of built-in training, repair and calibration.
eSilicon memory compilers expand the performance and density range with the combination of memory architectures designed for high speed such as the fast cache SP SRAM and DP SRAM compilers as well as the high-speed pseudo two-port.
The TCAM is an excellent choice for packet forwarding and classification in internet routers as well as in a variety of other applications that require high-speed table lookup. eSilicon’s TCAM provides performance of 2.5 billion searches per second (BSPS) under typical operating conditions with overdrive voltage and a latency of one clock cycle. TCAM performance is 1.25 giga searches per second (GSPS) under worst operating conditions. Such high-performance, low-latency TCAMs are critical for packet classification at wire speeds.
High-Speed Cache Compiler
eSilicon’s high-speed cache compiler is targeted to exceed 2.5GHz operation with small setup and hold times on the Address, Data, Bit Write, Memory Enable, and Write Enable input pins at worst-case conditions.
Pseudo Two-Port SRAM Compiler
The pseudo SRAM architecture is a high-density, low leakage alternative to traditional multi-port SRAMs constructed from foundry-supplied 6T SRAM bitcells. These memories are double-clocked internally to achieve multi-port functionality providing significant area reduction.
There are two pseudo two-port SRAM compilers: one optimized for high-speed running at 1.2GHz worst case and a high density running at 900MHz worst case. The pseudo SRAM architecture is a high-density, low-leakage alternative to traditional SRAMs. Pseudo SRAMs are multi-port memories constructed from regular single- or dual-port SRAMs. The pseudo SRAM architecture is double clocked internally to achieve multi-port functionality with significant area reduction as a result of incorporating smaller bitcells.
Two-Port Asynchronous Register File Compiler
The two-port asynchronous register file compiler offers speeds that exceed 2 GHz under typical operating conditions. This compiler architecture has an asynchronous READ and synchronous WRITE ports.
PPA-Optimized Memory IP
Our memories are optimized across the spectrum of performance, power, area, and yield to address customer-specific market requirements. eSilicon memories support industry-standard EDA flows. We work closely with our foundry and integrated device manufacturer (IDM) partners to incorporate the latest guidelines, including statistical analysis, design for manufacturability (DFM) rules, and redundancy guidelines. We collaborate with our customers to customize an already-developed memory compiler or instance and optimize the functionality, performance, power, area, or yield to match their SoC’s design-specific needs.
The EVGPIO Library contains a set of bi-directional I/O cells and all necessary analog, power-up, power, ground, corner, and filler cells. This library is designed to optimize I/O performance with a nominal core voltage and I/O supply voltages of 1.8V, 2.5V and 3.3V (typical case). This library is compliant with industry-standard ESD, LU and electrical guidelines.
Samsung 14LPP Technology
|Product Name||Key Feature||Foundry Sponsored||eSilicon Licensed||Front-End Design Kit||Back-End Design Kit|
|High-Speed SP TCAM||1.2GHz||X||Available||Available|
|Ultra-High-Speed SP TCAM||1.5GHz||X||Available||Available|
|High-Speed SP Fast Cache||2.5GHz||X||Available||Available|
|High-Speed DP SRAM||1.2GHz||X||Available||Available|
|High-Speed Pseudo 2-Port SRAM||1.2GHz||X||Available||Available|
|High-Density Pseudo 2-Port SRAM||Density||X||Available||Available|
|High-Density 2-Port Asynchronous RF||Async READ||X||Available||Available|
|Ultra-High-Speed Pseudo 2-Port SRAM||1.5GHz||X||Available||Mar-17|
|High-Speed Four-Port Register File||Multi-Port||X||Available||Aug-17|
|1.8V Oxide 1.8V/2.5V/3.3V General-Purpose I/O Library||X||Available||Available|
|1.8V Oxide 1.8V LVDSOUT I/O Library||X||Available||Available|
|1024 bit HBM2 PHY||2Gbps per bit||X||Available||Available|
TSMC 16FF Technologies
|Technology Variant||IP||Product Name||Front-End Design Kit||Back-End Design Kit|
|16FFC||Memory Compilers||High-Speed Single Port Ternary CAM (SP TCAM) Compiler||Available||Jun-17|
|I/O Library||Extended-Voltage 1.8V/2.5V/3.3V General-Purpose I/O Library||Available||Jun-17|
|16FF+GL||Memory Compilers||High-Speed Single-Port Ternary CAM (SP TCAM) Compiler||Available||Jul-17|
|High-Speed Dual-Port SRAM||Available||Available|
|High-Speed 2-Port Register File||Available||Available|
|I/O Library||Extended -Voltage 1.8V/2.5V/3.3V General-Purpose I/O Library||Available||Jun-17|
|16FF+LL||Memory Compiler||High-Speed Single-Port (SP TCAM) Ternary CAM Compiler||Available||Available|
All eSilicon IP is available through the TSMC9000 program.
For silicon quality report results, data sheets, white papers or information on these new memories, please contact us at firstname.lastname@example.org.