Custom 2.5D & 3D Packaging / HBM Solutions

Custom 2.5D & 3D Packaging /
HBM Solutions

Custom 2.5D Packaging

eSilicon has been in the forefront of 2.5D technology for years. Our first high-bandwidth memory 1 (HBM1) connected devices were assembled in 2013 and we have been active in the space since then with organic interposer technology, silicon interposer technology, non-interposer-based technologies and the IP needed to enable this technology.
eSilicon started the MoZAIC™ program (Modular Z-Axis Integrated Circuit) in 2011, focused on enabling the IP, design capability, packaging and test methodologies and supply chain needed to ensure the lowest-risk, highest-performance device development.

eSilicon HBM ASIC and FPGA 2.5D Projects on Silicon and Organic Interposers

HBM ASIC With Silicon Interposer 2015 HBM FPGA With Organic Interposer 2012
high-bandwidth memory (HBM) 2.5D asic on silicon interposer 2015 high-bandwidth memory (HBM) 2.5D FPGA on organic interposer
  • An industry first
  • Silicon interposer
  • 8 HBM interfaces
  • 28nm ASIC (11X17mm)
  • 850MHz
  • ARM core
  • All interconnect at 55um pitch
  • Targeted specifically for networking
  • An industry first
  • 38x30mm organic interposer
  • 50 percent larger than largest silicon interposer
  • 4 HBM interfaces
  • FPGA (24x19mm)
  • All interconnect at 55um pitch
  • Targeted specifically for networking

eSilicon HBM1 and HBM2 PHY, DLL and I/O Libraries

eSilicon also develops HBM Gen1 and HBM Gen2 PHY, DLL and I/O libraries, catering to a wide variety of customers and market segments from 28nm to 14nm/16nm. Our HBM Gen2 I/O library includes support for programmable driver strengths, embedded ESD/Decaps, internal programmable VREF generators, receiver power-down modes and can support up to 2Gb/s data rate with clock speeds of up to 1GHz.

Key features of eSilicon’s HBM Gen 2 PHY IP:

  • 1GHz operation with data rates of up to 2Gbps/pin
  • Support both 1:2 and 1:4 serialization/deserialization modes
  • Eight channels with 1024 DQs per HBM Gen 2 stack
  • Lower power I/O interface with unterminated DATA/ADDRESS/CMD/CLK interfaces
  • Pseudo-differential receiver with internal programmable VREF
  • One Read Strobe and one Write Strobe (RDQS/WDQS) for every 32 DQs (DWORD), one DBI/DM for every eight DQs, one parity bit for every DWORD
  • Write eye/Read eye training support
  • Built-in FSM for interface training
  • Programmable internal VREF generator support for fine tuning
  • Built-in status and control of configuration registers
  • Pseudo channel mode support

Please contact us at for HBM Gen1 and HBM Gen2 data sheets and other technical documentation or if you would like to learn more about our IP and I/O offerings.

eSilicon 2.5D Concept

2.5D ASIC concept drawing

eSilicon is connected to all levels of the semiconductor manufacturing supply chain: fabs, test and assembly companies, EDA companies and design houses. If you are interested in doing your first 2.5D or 3D project, we can help you make the right decisions. eSilicon will manage the entire supply chain using the fabs and assembly and test houses that are ready for 2.5D and 3D-ICs. eSilicon is already active in 2.5D and expects to be an early adopter of production-ready 3D technology.