Do you have a design that just doesn’t meet your power budget? Perhaps you can’t close timing, or fit in the package. These challenges are often due to a small number of challenging blocks in the design.
Thanks to eSilicon’s design virtualization technology, we can help. We analyze your challenging blocks to find the optimized operating point, VT mix, cell library or memory choice that will address your challenges.
All with a pay-for-results, no-risk engagement.
How it Works
First, we will send you a free, automated script to check your design to ensure it is optimization-ready. This script will check for design consistency and robustness and provide a report. If you get a “green light” from the script, we proceed to the specification stage, where we define the required optimization targets (power, performance, area).
We then use our design virtualization technology to analyze your design and find the configuration that will address your needs.
Optimal IC Implementations
Example Results of a Design Optimization Process
|Technology||Industry 28nm Process||Alternative A||Alternative B||Alternative C||Alternative D|
|Speed||Target same speed|
|Voltage||1V ± 0.1V||0.9V± 0.1V||1V ± 0.1V||1V ± 0.1V||1V ± 0.1V|
|Standard cell library||30nm SVT and LVT||30nm LVT||40nm LVT||30nm SVT||35nm SVT and LVT|
|Leakage Power (FF, Vmax, 125C)||1.29W||657mW||2.06W||650mW||1.25W|
|Dynamic Power (TT, Vnom, 25C)||756mW||663mW||971mW||670mW||1.05W|
Let eSilicon help you find your optimal implementation path, risk-free. Contact us at STAR@eSilicon.com to learn more.