Multi-Project Wafer Tapeout Process & Support

eSilicon MPW Tapeout Process and Support

Our multi-project wafer (MPW) services process is as follows:

1. After you complete the online MPW quote form, you will receive a confirmation email. The email will, unless there are questions or issues, contain your MPW quote and your eSilicon contact/sales manager details. Upon receipt, please email the following information to your eSilicon contact/sales manager:

  • Signed quote (PDF)
  • Purchase order (PDF)
  • Signed NDA (PDF)
  • Completed export questionnaire (PDF)
  • Your estimated date for tapeout based on the foundry tapeout schedule for the specific technology you are using. Please check the shuttle calendar using the link above the MPW quote request form.

2. After eSilicon receives your signed quote and returns a fully signed quote, you will receive an email with secure FTP access details. Please upload the following information to eSilicon’s FTP site at least three weeks before tapeout:

  • GDSII database
  • Case-sensitive top-level structure name
  • Lower-left and upper-right corner coordinates of the actual GDS structure, related to the GDS 0,0 origin
  • DRC/ANT/ERC/LVS reports and waivers, if appropriate
  • Specify if the seal ring is already included or if it will be automatically placed by the foundry
  • Special characteristics of layers (such as aluminum thickness, MIM/MOM capacitors, etc.)
  • Bit-cell size for memories
  • GDS layer mapping
  • Bench/verification report
  • Metal stack definition
  • SRAM bit cell
  • Any special IP included
  • Any merge included
  • Core and I/O voltages
  • Number of bits in the design
  • Sign-off decks, command decks and version
  • Number of bumps (flip chip only)
  • Bump pitch and opening data (flip chip only)
  • Special CAD layer usage
  • SRAM orientation
  • List of all optional devices not part of the baseline
  • Whether or not the part can be rotated in the reticle

3. eSilicon will transfer the files to the foundry and manage all fab-related activities. If any issues come up, an eSilicon process engineer will contact you seeking the appropriate information.

4. Please send a preliminary database at least two weeks before the scheduled tapeout (does not have to be LVS/DRC clean) so eSilicon can do a visual inspection of the database and validate the CAD layer usage.

5. Please send the final GDSII (DRC/LVS clean) at least two days before the scheduled tapeout date

6. eSilicon will quote DRC services per customer request.

7. Before tapeout, eSilicon will send a customer acknowledgement form to confirm the tapeout details.

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