2.5D/HBM2 Packaging & Solutions

Industry-Leading Custom 2.5D Solutions

eSilicon started the MoZAIC™ “Modular Z-axis Integrated Circuit” Program in 2011. As an ASIC provider for large, complex networking, communication and computing systems, we began analyzing new approaches that would provide more bandwidth for our customers.

This includes the development of an HBM PHY in 28nm and finFET technologies as well as the study of 2.5D packaging. eSilicon has completed seven test chips to date that verify the HBM PHY IP and assemble a supply chain in support of 2.5D integration — design, verification, test and reliability.

eSilicon has multiple 14/16nm finFET 2.5D ASICs in design, with several entering production in 2018.

eSilicon 2.5D Concept

2.5D ASIC concept drawing

eSilicon HBM ASIC and FPGA 2.5D Projects on Silicon and Organic Interposers

HBM ASIC With Silicon Interposer 2015 HBM FPGA With Organic Interposer 2012
high-bandwidth memory (HBM) 2.5D asic on silicon interposer 2015 high-bandwidth memory (HBM) 2.5D FPGA on organic interposer
  • An industry first
  • Silicon interposer
  • 8 HBM interfaces
  • 28nm ASIC (11X17mm)
  • 850MHz
  • ARM core
  • All interconnect at 55um pitch
  • Targeted specifically for networking
  • An industry first
  • 38x30mm organic interposer
  • 50 percent larger than largest silicon interposer
  • 4 HBM interfaces
  • FPGA (24x19mm)
  • All interconnect at 55um pitch
  • Targeted specifically for networking

Comprehensive 2.5D Design & Implementation

  • 2.5D ecosystem management
  • 2.5D interposer and package design
  • Interposer and package routing
  • Design for manufacturability (DFM)
  • Signal integrity/power integrity design and analysis
  • Thermal integrity
  • Warpage analysis
  • Single production source for:
    • Acquisition/assignment of all die in package
    • Assembly
    • Test
    • Delivery of final, tested, yielded devices

eSilicon HBM GEN2 PHY and Controller

eSilicon also develops a hardened HBM PHY, catering to a wide variety of customers and market segments from 28nm to 10nm. Through our partnership with Northwest Logic, we offer a comprehensive HBM interface including both the controller and the PHY, which is silicon validated in an integrated system that includes the interposer and DRAM stack.

Key features of eSilicon’s HBM Gen2 PHY IP:

  • 1GHz operation with data rates of up to 2Gbps/pin
  • Support both 1:2 and 1:4 serialization/deserialization modes
  • Eight channels with 1024 DQs per HBM Gen2 stack
  • Lower power I/O interface with unterminated DATA/ADDRESS/CMD/CLK interfaces
  • Pseudo-differential receiver with internal programmable VREF
  • One Read Strobe and one Write Strobe (RDQS/WDQS) for every 32 DQs (DWORD), one DBI/DM for every eight DQs, one parity bit for every DWORD
  • Write eye/Read eye training support
  • Built-in FSM for interface training
  • Programmable internal VREF generator support for fine tuning
  • Built-in status and control of configuration registers
  • Pseudo channel mode support

Please contact us at sales@esilicon.com for HBM Gen1 and HBM Gen2 data sheets and other technical documentation or if you would like to learn more about our IP and I/O offerings.

eSilicon is connected to all levels of the semiconductor manufacturing supply chain: fabs, test and assembly companies, EDA companies and design houses. If you are interested in doing your first 2.5D or 3D project, we can help you make the right decisions. eSilicon will manage the entire supply chain using the fabs and assembly and test houses that are ready for 2.5D and 3D ICs.