Design Virtualization

IC Design Virtualization

At advanced technology nodes (40nm and below), the number of options that an SoC designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply no way to run the required number of trial implementations to ensure the best possible option choices.

Options Faced by the SoC Designer

IC designers are faced with many ASIC options
It’s impractical for IC designers to evaluate all ASIC options.

 

Design virtualization technology is a solution that allows a large number of alternative approaches to the design to be explored with a view to picking one that best matches the system requirements. Design virtualization technology is a layer between the design and the implementation technology. It allows optimization of the design by considering alternative implementation choices, such as libraries, voltages, power-supply tolerances and temperature limits.

The IT industry has changed the model for delivery of end user applications through the use of virtualization layer to free the developer from specific hardware/software constraints. Design virtualization promises to do the same thing for delivery of complex system on chip (SoC) devices. The designer is now free to explore multiple options without the need for time-consuming and costly implementation trials. Design virtualization delivers the required information quickly and accurately.

Design Virtualization: Traditional vs. Virtualized Design Flows

 

Traditional Flow

design-virtualization-flow-before

  • All chip “recipe” decisions made up front
  • No visibility into consequences of decisions
  • Inefficient, inflexible implementation

Virtualized Flow

design-virtualization-flow-after

  • Chip “recipe” chosen throughout the process
  • Full visibility into impact of decisions on Power, Performance, and Area (PPA)
  • Optimized implementation, predictable results

At its core, design virtualization technology utilizes big data strategies to capture engineering knowledge from suppliers worldwide regarding how process options, IP, foundation libraries, memory architectures and operating conditions interact with each other to impact the power, performance and area (PPA) of a system-on-chip (SoC) design. This information is accessed through the cloud and provides real-time, predictive analysis to guide the optimal choice for all these variables.

In many cases, there is time for only one major design iteration for the SoC. Taking longer will result in a missed market window and dramatically lower market share and revenue. This backdrop creates a rich set of opportunities for technology to reduce risk and improve results. The real-time predictive analysis technology delivered by design virtualization provides a new and powerful tool to address these challenges.

Commercial electronic design automation (EDA) tools are intended to build the best SoC possible given a fixed set of choices. What is needed is the ability to optimize these choices before design begins and throughout the design process as well. With this optimization, EDA technology and SoC design teams are better able to deliver the best result possible.

The ability to explore the broader solution space for each design is now within reach of all design teams thanks to the big data analytics and deep machine learning employed by design virtualization.

eSilicon STAR Design Virtualization Platform

The eSilicon® STAR design virtualization platform is a self-service, transparent, accurate, real-time ASIC design and delivery environment using eSilicon smart tools and big data on a secure cloud platform. The STAR online design virtualization platform helps you manage complexity and make the right decisions on your ASIC journey from concept to volume production.

Our engineers have developed proprietary technology for design virtualization, based on big data analytics and deep machine learning. They have continually refined this technology through more than 300 customer engagements with first-time-right results.

The eSilicon STAR online tool suite includes:

Navigator: Search, select and try IP online

Optimizer: Versatile self-service IC design optimization for power, performance or area

Explorer: Evaluate options and get fast, accurate quotes for multi-project wafer (MPW) shuttle services and GDSII handoffs

Tracker: Real-time design progress and IC delivery tracking, including order history, forecasts and yield data

STAR tools are available at no charge or obligation.