28nm High-Performance, Low-Power Three-Way Microprocessor Cluster for Embedded Platforms
eSilicon and MIPS Technologies have jointly developed a high-performance, three-way microprocessor cluster on GLOBALFOUNDRIES’ leading-edge, low-power 28nm-SLP process technology. Wafers are currently running in Fab 1 in Dresden, Germany, with silicon expected in early 2012. SoC designs using the hard macro of the cluster can start immediately.
MIPS provided the RTL based on its leading-edge MIPS32® 1074Kf™ Coherent Processing System (CPS), and eSilicon performed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1GHz for the cluster. Typical performance is expected to be approximately 1.5GHz.
To reach the 1GHz target without compromising low power, eSilicon’s custom memory team created custom fast cache instances (FCIs) for the L1 caches to replace standard memories that were in the critical path of the design. The 1074Kf CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, Out-of-Order (OoO) MIPS32 74K processor core as the base CPU. The 74K core is a multi-issue, 15-stage OoO architecture already in production with numerous customers for digital televisions, set-top boxes and a variety of home networking applications. It is broadly used in internet-connected digital home products.
Customers can license the 1GHz implementation from eSilicon today—either as is or customized. The cluster has been taped out as a test chip, and will be offered as a hard macro core. It includes embedded design-for-test (DFT) and design-for-manufacturing (DFM) features so that it can be dropped into a chip design and used without modification. As part of a full SoC development, it can be further customized and optimized to meet the specific needs of the application.
- Highest-performance MIPS core in a low-power process
- Performance proven over process corners and conditions
- Integrated, cost-effective solution
- Three cores
- L1 and L2 cache
- Coherency Manager
- All DFT circuitry
- Low-risk integration, with reduced time to market
- Allows your engineering team to focus on differentiating hardware and application requirements
Some of the key applications for this 28nm 1.5GHz microprocessor cluster include:
- Internet-connected multimedia products such as DTVs, Blu-ray players and set-top boxes
- Home/wireless networking products
- Android tablets
The cluster is available now as a hard macro in the GLOBALFOUNDRIES 28nm SLP process.
Customization is available as required:
- Higher-performance, lower-power versions
- Porting to other process variants
- Modifications to configuration — different cache sizes or numbers of cores in the cluster
- Full sub-system including peripherals
Hard Macro Core and Custom IP Engagement Details
- The RTL can be licensed from MIPS or from eSilicon
- The hard macro can be licensed from eSilicon – either for use in an eSilicon ASIC or for use elsewhere
- eSilicon can drop the macro directly into designs built on the GLOBALFOUNDRIES 28nm SLP process
- Customization services are available from eSilicon for other processes and to optimize to meet specific application needs:
- Very competitive license fee and royalty
- eSilicon will also be making the macro available as a “Tile” for use in 2.5D packages
Please contact us at
or 877-769-2447 for full details on this new core.
Hard IP Core Design Kit and Specifications
1074Kf Hard Macro
Process: 28nm SLP process from GLOBALFOUNDRIES
Performance: 1.0 GHz worst-case, 1.5GHz typical*
Caches: 32K/32K L1 cache, 1MB L2 cache
* Subject to silicon verification
Hard IP Core Design Kit
Hard IP cores are delivered with a design kit that includes the necessary components for development of a complete SoC:
- Core documentation
- Core design data
- Core verification and simulation models
- User manual
- Installation instructions
- All operational modes
- Revision control updates
- All EDA views
- Instance-specific datasheets
- Timing and power models
- Layout models
- Layout manufacturing data
- LVS netlist
- Layout parameter extraction data
More IP Solutions
If you'd like more information on these offerings, our pre-hardened ARM IP cores, or have questions about other IP not featured here, please contact us. eSilicon has an extensive database of semiconductor IP, as well as custom IP capabilities, and can help find the right IP for your custom chip.