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Webinar Video:
10-Minute GDSII
Tapeout Quotes

Replay of a live eSilicon webinar moderated by Dan Nenni (SemiWiki founder) where we demonstrate our GDSII quoting portal.  Working with a real customer, we generate a complete, executable quotation for a production GDSII tapeout at TSMC in about 10 minutes.  We also explore "what if" scenarios to optimize unit price for the program. Created: July 31, 2014, 8:00 AM PDT.

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TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

Request a copy of this application note by email.

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Instant MPW Quotes: New Die Packaging Services

Request a free account and explore your multi-project wafer (MPW) production options with no obligation. Our newest MPW quoting tool includes standard IC package options.
MPW shuttle service details>>>

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See Our Complete
IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

Published Books by eSilicon's Technical Staff

An ASIC Low-Power Primer

asic-low-power-primer-by-j-bhasker-and-rakesh-chadha-of-esilicon-150x225px

An ASIC Low-Power Primer, by eSilicon engineers Dr. J. Bhasker, architect, and Dr. Rakesh Chadha, director of design technology, provides invaluable training on design techniques for low-power digital semiconductor devices.

"System power management is a critical aspect of IC design — everyone cares about low-power design in order to be green; it is no longer the domain of mobile applications. Power management spans technology, standard cell library and memory selection, IP design, RTL design and physical implementation," said Dr. Prasad Subramaniam, eSilicon's vice president of design technology. "This book covers all these topics. And it would be difficult to find a better source than eSilicon and Rakesh and Bhasker who have extensive experience with power management and low-power IC design over multiple generations of technologies."

The authors guide readers through architectural and implementation techniques, system power consumption analysis, low-power design techniques and more. The duo also wrote Static Timing Analysis for Nanometer Designs: A Practical Approach (see below).

An ASIC Low-Power Primer is now available from Springer, a leading publisher of science and technology reference books, as well as Amazon.

Other books by Jayaram Bhasker and by Rakesh Chadha are also available on Amazon.

A System Verilog Primer

A System Verilog Primer, by Jayaram Bhasker

A System Verilog Primer, by Jayaram Bhasker, is a practical and concise guide for designing RTL synthesizable models in Verilog providing readers with the knowledge to begin writing synthesizable Verilog models quickly and with confidence.

Jayaram Bhasker is a distinguished author and expert in the area of hardware description languages and RTL synthesis. He is an architect at eSilicon Corporation.

To order A System Verilog Primer or to read reviews go to Amazon.

Other books by Jayaram Bhasker are also available on Amazon.

Static Timing Analysis for Nanometer Designs: A Practical Approach

Static Timing Analysis for Nanometer Designs: A Practical Approach

Static Timing Analysis for Nanometer Designs: A Practical Approach, co-authored by Jayaram Bhasker and Rakesh Chadha, is written for professionals working in the area of chip design and timing verification of ASICs. The book covers topics such as cell timing and power modeling; interconnect modeling, delay calculation, crosstalk and other relevant issues.

Jayaram Bhasker is an architect at eSilicon Corporation. Rakesh Chadha is the director of design technology at eSilicon Corporation.

To order Static Timing Analysis for Nanometer Designs: A Practical Approach, or to read reviews, go to Amazon.

Other books by Rakesh Chadha are also available on Amazon.


Computer-aided Design of Microwave Circuits

Computer-aided Design of Microwave Circuits

Computer-aided Design of Microwave Circuits, Rakesh Chadha with K.C. Gupta and Ramesh Garg, Artech House Publishers, 1981, ISBN 0-89006-106-8. (Also published in Chinese and Russian)

Rakesh Chadha is the director of design technology at eSilicon Corporation.

To order Computer-aided Design of Microwave Circuits, or to read reviews, go to Amazon.


The Exchange Format Handbook: A DEF, LEF, PDEF, SDF, SPEF & VCD Primer

The Exchange Format Handbook: A DEF, LEF, PDEF, SDF, SPEF & VCD Primer

The Exchange Format Handbook: A DEF, LEF, PDEF, SDF, SPEF & VCD Primer, Jayaram Bhasker, Star Galaxy Publishing, Allentown, PA, 2006, ISBN 0-9650391-3-7
(Also published in Chinese)

A SystemC Primer

A SystemC Primer

A SystemC Primer, Jayaram Bhasker, Second Edition, Star Galaxy Publishing, Allentown, PA, 2004, ISBN 0-9650391-2-9 (First edition, 2002, ISBN 0-9650391-8-8) (Published in Chinese)

A VHDL Primer

A VHDL Primer

A VHDL Primer, Third Edition ,Jayaram Bhasker, Prentice Hall, Englewood Cliffs, NJ, 1999, ISBN 0-13-096575-8 (Second edition, 1995, ISBN 0-13-181447-8; First edition, 1992, ISBN 0-13-952987-X) (Also published in Japanese)

Verilog HDL Synthesis, A Practical Primer

Verilog HDL Synthesis, A Practical Primer

Verilog HDL Synthesis, A Practical Primer, Jayaram Bhasker, Star Galaxy Publishing, Allentown, PA, 1998, ISBN 0-9650391-5-3 (Indian edition, BS Publications, 2001, ISBN 81-7800-011-3).

A Guide to VHDL Syntax

A Guide to VHDL Syntax

A Guide to VHDL Syntax, Jayaram Bhasker, Prentice Hall, Englewood Cliffs, NJ, 1995, ISBN 0-13-324351-6.
(Also published in German) VHDL Features and Applications: Study Guide, IEEE, 1995, Order No. HL5712.