TCAM Application Note: Streamline Multi-Byte Searches With TCAM Arrays

Embedded content addressable memories (CAMs) allow system designers to define various configurations to match architectural requirements to achieve the optimal performance, power and cost of the system.

This application note describes a simple way to customize eSilicon’s eFlexCAM™ memories into a register-array CAM that supports parallel compare and write operations and multiple byte-match lines, typically used in network security applications.

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White Paper

High-Performance Classification Using Embedded Ternary Content Addressable Memory (TCAM)

With port speeds exceeding 100Gbps, route lookups that are a fundamental application to all routers have relied on ternary content addressable memories (TCAM) to provide a lookup response within a clock cycle. However, these devices in “discrete form” suffer from limitations in terms of power, cost and real estate and to some extent lack the required flexibility. Embedding a TCAM block along with the rest of the system in a single device should overcome these disadvantages. This paper provides an overview of advantages of embedded TCAMs and describes a few applications that could take advantage of embedded TCAM technology. [View more white papers]

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IP Catalog

Our complete portfolio of customizable semiconductor IP and I/Os is available at ChipEstimate.com.

Custom Embedded IP Brochures

eFlexCAM™ Custom Embedded
CAM Compilers

Binary and Ternary CAM (BCAM and TCAM) compilers in 28nm-180nm.

eFlex™ Custom Embedded
Memory IP

SRAM, ROM, MPRF, CAM, and cache custom memories.

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Specialty Register Files

Multi-Port Register Files

eSilicon has designed four-port register file memory compilers catering to multiple customers in the networking and communications domains. These memories have two write ports and two read ports.

eSilicon four-port register files are now available in 28nm, 40nm and 65nm geometries through eSilicon. eSilicon is a member of the TSMC IP Alliance program and these IPs are currently undergoing TSMC9000™ assessment.

Features

  • Speeds in excess of 2 GHz, typical operating conditions, TSMC 28nm HPM technology
  • Two independent read ports and two independent write ports
  • Supports parallel operations to increase system bandwidth
  • Zero clock latency overhead
  • Deterministic timing
  • Easily integrates on chip with existing design flows

Availability

eSilicon 28nm four-port register files are available now. Silicon results and data sheets are available from This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Networking and communications customers have long relied on the performance of eSilicon's high-speed register files to meet the demanding wireline speed requirements of their tier-one customers.

Asynchronous Register File

eSilicon has designed asynchronous register file memory compilers catering to multiple customers in the networking and communications domains. These memories have one synchronous write port and one asynchronous read port.

Our 28nm asynchronous register files are available now through eSilicon. eSilicon is a member of the TSMC IP Alliance Program and these IPs are currently undergoing TSMC9000™ assessment.

Features

  • Read speeds in excess of 2.5 GHz, typical operating conditions, TSMC 28nm HPM technology
  • Independent write port and independent asynchronous read port
  • Enables fast access times for downstream operation.

Availability

eSilicon 28nm asynchronous register files are available now. Silicon results and data sheets are available from This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

eSilicon's philosophy for developing memories is to customize the specialty register file memory compilers, such as four-port register files and asynchronous register files, to end-customer requirements. This usually involves turning multiple knobs to fine-tune the performance, power or area of register files to customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.

Area

Performance

Power Management

Testability

Functional Options

  • Aspect Ratio
  • Side Decode
  • Low Vt for Highest Performance
  • Banking
  • Center Decode
  • Support over-drive voltage
  • DVFS
  • Mixed Vt Periphery
  • BIST Mux
  • Scan Flops
  • Synchronous Bypass
  • Read Stress
  • Write Stress
  • Bit Write

Please contact us at This e-mail address is being protected from spambots. You need JavaScript enabled to view it if you would like to learn more about our custom IP offering.