Specialty Register Files
Multi-Port Register Files
eSilicon has designed four-port register file memory compilers catering to multiple customers in the networking and communications domains. These memories have two write ports and two read ports.
eSilicon four-port register files are now available in 28nm, 40nm and 65nm geometries through eSilicon. eSilicon is a member of the TSMC IP Alliance program and these IPs are currently undergoing TSMC9000™ assessment.
Features
- Speeds in excess of 2 GHz, typical operating conditions, TSMC 28nm HPM technology
- Two independent read ports and two independent write ports
- Supports parallel operations to increase system bandwidth
- Zero clock latency overhead
- Deterministic timing
- Easily integrates on chip with existing design flows
Availability
eSilicon 28nm four-port register files are available now. Silicon results and data sheets are available from
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.
Networking and communications customers have long relied on the performance of eSilicon's high-speed register files to meet the demanding wireline speed requirements of their tier-one customers.
Asynchronous Register File
eSilicon has designed asynchronous register file memory compilers catering to multiple customers in the networking and communications domains. These memories have one synchronous write port and one asynchronous read port.
Our 28nm asynchronous register files are available now through eSilicon. eSilicon is a member of the TSMC IP Alliance Program and these IPs are currently undergoing TSMC9000™ assessment.
Features
- Read speeds in excess of 2.5 GHz, typical operating conditions, TSMC 28nm HPM technology
- Independent write port and independent asynchronous read port
- Enables fast access times for downstream operation.
Availability
eSilicon 28nm asynchronous register files are available now. Silicon results and data sheets are available from
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.
eSilicon's philosophy for developing memories is to customize the specialty register file memory compilers, such as four-port register files and asynchronous register files, to end-customer requirements. This usually involves turning multiple knobs to fine-tune the performance, power or area of register files to customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.
Area
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Performance
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Power Management
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Testability
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Functional Options
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- Low Vt for Highest Performance
- Banking
- Center Decode
- Support over-drive voltage
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- BIST Mux
- Scan Flops
- Synchronous Bypass
- Read Stress
- Write Stress
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Please contact us at
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if you would like to learn more about our custom IP offering.
