eSilicon started the MoZAIC™ (Modular Z-axis Integrated Circuit) Program in 2011. As an ASIC provider for large, complex networking, communication, computing and deep learning systems, we began analyzing new approaches that would provide more bandwidth for our customers.
This includes the development of a high-bandwidth memory (HBM/HBM2) PHYs in 28, 14/16 and 7nm technologies as well as proficiency in 2.5D packaging. eSilicon has completed multiple test chips to date that verify the HBM PHY IP, as well as assembled a supply chain in support of 2.5D integration — design, verification, test and reliability.
eSilicon has multiple FinFET 2.5D ASICs in design, with several entering production in 2019.
Example eSilicon HBM2/2.5D ASIC Design
Our hardened HBM2 PHY was designed to support a wide variety of OEM customers in high-performance market segments from 28nm to 7nm. Through our partnership with Northwest Logic, we offer a comprehensive HBM interface including both the controller and the PHY, which is silicon validated in an integrated system that includes the interposer and DRAM stack.
eSilicon’s 7nm HBM2E/HBM2 PHY is available now for licensing. Please contact firstname.lastname@example.org.
eSilicon recently announced the tapeout of a 7nm test chip to provide silicon validation of its PHY to support the new JEDEC standard JESD235B, referred to informally as HBM2E and emerging low-latency HBM (LLHBM) technology. The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic. This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.
|Data Rate||0.1-3.2Gbps per I/O|
|Channels||8 independent channels|
|Self-Refresh||Supported through memory controller|
|I/O per Channel||212|
|Bandwidth per Stack||Up to 409.6GB/s|
|Data I/O||128 per channel, 8 channels and 16 pseudo channels|
|ECC||ECC and parity support in conjunction with the controller. (ECC on DM signals)|
|Data Byte Invert (DBI)||DBI supported in conjunction with the controller|
|Data Mask (DM)||DM supported in conjunction with the controller|
|RAS Support||RAS supported in conjunction with the controller|
|Cycles/Command||1 cycle (exception is Row Activate at 2 cycles) per JEDEC specification|
|Interoperability Testing||Supports any third-party DFI 4.0-compliant memory controller vendor|
|IEEE1500 Support||Separate IEEE1500 port for direct access to the memory stack and PHY|
|Impedance Calibration Sharing||Self-contained calibration per PHY instance across all eight channels|
|Power-Down Modes||IDDQ MODE and dynamic power-down of receivers during WRITE|
|Functional Temperature Range (Tj)||-40C to 125C|
Please contact us at email@example.com for more information, silicon quality results, white papers, complete data sheets, design kits or front-end views.
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.
Additional details on our high-performance offering can be found in our 7nm IP Platform, Ternary CAM and HBM2 PHY brochures.
Our newest HBM white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, is available online: Start Your HBM/2.5D Design Today.
You may also be interested in our Advanced ASIC Video Series: